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6289766cd1
This patch add a support of ISD::ZERO_EXTEND in PPCDAGToDAGISel::tryBitPermutation to increase the opportunity to use rotate-and-mask by reordering ZEXT and ANDI.
Since tryBitPermutation stops analyzing nodes if it hits a ZEXT node while traversing SDNodes, we want to avoid ZEXT between two nodes that can be folded into a rotate-and-mask instruction.
For example, we allow these nodes
t9: i32 = add t7, Constant:i32<1>
t11: i32 = and t9, Constant:i32<255>
t12: i64 = zero_extend t11
t14: i64 = shl t12, Constant:i64<2>
to be folded into a rotate-and-mask instruction.
Such case often happens in array accesses with logical AND operation in the index, e.g. array[i & 0xFF];
Differential Revision: https://reviews.llvm.org/D37514
llvm-svn: 314655
24 lines
839 B
LLVM
24 lines
839 B
LLVM
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu | FileCheck %s
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; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s
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; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s
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; Test case for PPCTargetLowering::extendSubTreeForBitPermutation.
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; We expect mask and rotate are folded into a rlwinm instruction.
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define zeroext i32 @func(i32* %p, i32 zeroext %i) {
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; CHECK-LABEL: @func
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; CHECK: addi [[REG1:[0-9]+]], 4, 1
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; CHECK: rlwinm [[REG2:[0-9]+]], [[REG1]], 2, 22, 29
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; CHECK-NOT: sldi
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; CHECK: lwzx 3, 3, [[REG2]]
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; CHECK: blr
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entry:
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%add = add i32 %i, 1
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%and = and i32 %add, 255
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%idxprom = zext i32 %and to i64
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%arrayidx = getelementptr inbounds i32, i32* %p, i64 %idxprom
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%0 = load i32, i32* %arrayidx, align 4
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ret i32 %0
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}
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