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7118b8a8dd
optimizations As discussed in the thread http://lists.llvm.org/pipermail/llvm-dev/2020-May/141838.html, some bit field access width can be reduced by ReduceLoadOpStoreWidth, some can't. If two accesses are very close, and the first access width is reduced, the second is not. Then the wide load of second access will be stalled for long time. This patch add command line options to guard ReduceLoadOpStoreWidth and ShrinkLoadReplaceStoreWithStore, so users can use them to disable these store width reduction optimizations. Differential Revision: https://reviews.llvm.org/D80745
19 lines
577 B
LLVM
19 lines
577 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-- -combiner-shrink-load-replace-store-with-store=false | FileCheck %s
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define void @shrink(i16* %ptr) {
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; CHECK-LABEL: shrink:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movzbl (%rdi), %eax
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; CHECK-NEXT: orl $25600, %eax # imm = 0x6400
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; CHECK-NEXT: movw %ax, (%rdi)
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; CHECK-NEXT: retq
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entry:
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%val = load i16, i16* %ptr
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%masked_val = and i16 %val, 255
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%replaced_val = or i16 %masked_val, 25600
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store i16 %replaced_val, i16* %ptr
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ret void
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}
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