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llvm-mirror/test/CodeGen/X86/implicit-null-chk-reg-rewrite.mir
Guillaume Chatelet d49cb60862 [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing
Summary:
This catches malformed mir files which specify alignment as log2 instead of pow2.
See https://reviews.llvm.org/D65945 for reference,

This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

Reviewers: courbet

Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67433

llvm-svn: 371608
2019-09-11 11:16:48 +00:00

50 lines
973 B
YAML

# RUN: llc -mtriple=x86_64 -run-pass=implicit-null-checks %s -o - | FileCheck %s
--- |
define i32 @reg-rewrite(i32* %x) {
entry:
br i1 undef, label %is_null, label %not_null, !make.implicit !0
is_null:
ret i32 42
not_null:
ret i32 100
}
!0 = !{}
...
---
# Check that the TEST instruction is replaced with
# FAULTING_OP only if there are no instructions
# between the TEST and conditional jump
# that clobber the register used in TEST.
name: reg-rewrite
alignment: 16
tracksRegLiveness: true
liveins:
- { reg: '$rdi' }
body: |
bb.0.entry:
liveins: $rdi
TEST64rr $rdi, $rdi, implicit-def $eflags
; CHECK-LABEL: bb.0.entry
; CHECK-NOT: FAULTING_OP
renamable $rdi = MOV64ri 5000
JCC_1 %bb.2, 4, implicit $eflags
bb.1.not_null:
liveins: $rdi, $rsi
$rax = MOV64rm renamable $rdi, 1, $noreg, 4, $noreg
RETQ $eax
bb.2.is_null:
$eax = MOV32ri 200
RETQ $eax
...