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7d16c968d5
SAHF/LAHF instructions are always available in 32-bit mode. Early 64-bit capable CPUs made the undefined opcodes in 64-bit mode. This was changed on later CPUs. We have a feature flag to control our usage of these instructions. This feature flag is hooked up to a clang command line option -msahf/-mno-sahf specifically to give control of the 64-bit mode behavior. In the backend X86Subtarget constructor we were explicitly forcing +sahf into the feature flag string if we were not compiling for 64-bit mode. This was intended to make the predicates always allow the instructions outside of 64-bit mode. Unfortunately, the way it was placed into the string allowed -mno-sahf from clang to disable SAHF instructions in 32-bit mode. This causes an assertion to fire if you compile a floating point comparison with something like "-march=pentium -mno-sahf" as our floating point comparison handling on CPUs that don't support FCOMI/FUCOMI instructions requires SAHF. To fix this, this commit restricts the feature flag to only apply to 64-bit mode by ignoring the flag outside 64-bit mode in X86Subtarget::hasLAHFSAHF(). This way we don't need to mess with the feature string at all.
34 lines
1.2 KiB
LLVM
34 lines
1.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-- | FileCheck %s
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; Sanity check that we ignore -sahf in 32-bit mode rather than asserting.
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; RUN: llc < %s -mtriple=i686-- -mattr=-sahf | FileCheck %s
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declare i1 @llvm.isunordered.f32(float, float)
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define float @cmp(float %A, float %B, float %C, float %D) nounwind {
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; CHECK-LABEL: cmp:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: flds {{[0-9]+}}(%esp)
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; CHECK-NEXT: flds {{[0-9]+}}(%esp)
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; CHECK-NEXT: fucompp
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; CHECK-NEXT: fnstsw %ax
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; CHECK-NEXT: # kill: def $ah killed $ah killed $ax
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; CHECK-NEXT: sahf
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; CHECK-NEXT: jbe .LBB0_1
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; CHECK-NEXT: # %bb.2: # %entry
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; CHECK-NEXT: leal {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: flds (%eax)
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; CHECK-NEXT: retl
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; CHECK-NEXT: .LBB0_1:
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; CHECK-NEXT: leal {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: flds (%eax)
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; CHECK-NEXT: retl
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entry:
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%tmp.1 = fcmp uno float %A, %B ; <i1> [#uses=1]
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%tmp.2 = fcmp oge float %A, %B ; <i1> [#uses=1]
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%tmp.3 = or i1 %tmp.1, %tmp.2 ; <i1> [#uses=1]
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%tmp.4 = select i1 %tmp.3, float %C, float %D ; <float> [#uses=1]
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ret float %tmp.4
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}
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