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1e2065572a
This function has a bug which will incorrectly reschedule instructions after an INLINEASM_BR (which can branch). (The bug may also allow scheduling past a throwing-CALL, I'm not certain.) I could fix that bug, but, as the removed FIXME notes, it's better to attempt rescheduling before converting to 3-addr form, as that may remove the need to convert in the first place. In fact, the code to do such reordering was added to this pass only a few months later, in 2011, via the addition of the function rescheduleMIBelowKill. That code does not contain the same bug. The removal of the sink3AddrInstruction function is not a no-op: in some cases it would move an instruction post-conversion, when rescheduleMIBelowKill would not move the instruction pre-converison. However, this does not appear to be important: the machine instruction scheduler can reorder the after-conversion instructions, in any case. This patch fixes a kernel panic 4.4 LTS x86_64 Linux kernels, when built with clang after 4b0aa5724feaa89a9538dcab97e018110b0e4bc3. Link: https://github.com/ClangBuiltLinux/linux/issues/1085 Differential Revision: https://reviews.llvm.org/D83708
105 lines
2.6 KiB
LLVM
105 lines
2.6 KiB
LLVM
;; X's live range extends beyond the shift, so the register allocator
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;; cannot coalesce it with Y. Because of this, a copy needs to be
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;; emitted before the shift to save the register value before it is
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;; clobbered. However, this copy is not needed if the register
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;; allocator turns the shift into an LEA. This also occurs for ADD.
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; Check that the shift gets turned into an LEA.
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; RUN: llc < %s -mcpu=generic -mtriple=x86_64-apple-darwin | FileCheck %s
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@G = external global i32
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define i32 @test1(i32 %X) nounwind {
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; CHECK-LABEL: test1:
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; CHECK: movl %edi, %eax
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; CHECK: leal 1(%rax)
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%Z = add i32 %X, 1
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store volatile i32 %Z, i32* @G
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ret i32 %X
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}
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; rdar://8977508
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; The second add should not be transformed to leal nor should it be
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; commutted (which would require inserting a copy).
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define i32 @test2(i32 inreg %a, i32 inreg %b, i32 %c, i32 %d) nounwind {
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entry:
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; CHECK-LABEL: test2:
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; CHECK: leal
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; CHECK-NEXT: addl
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; CHECK-NEXT: addl
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; CHECK-NEXT: ret
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%add = add i32 %b, %a
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%add3 = add i32 %add, %c
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%add5 = add i32 %add3, %d
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ret i32 %add5
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}
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; rdar://9002648
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define i64 @test3(i64 %x) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: test3:
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; CHECK: leaq (%rdi,%rdi), %rax
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; CHECK-NOT: addq
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; CHECK-NEXT: ret
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%0 = shl i64 %x, 1
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ret i64 %0
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}
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@global = external global i32, align 4
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@global2 = external global i64, align 8
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; Test that liveness is properly updated and we do not encounter the
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; assert/crash from http://llvm.org/PR28301
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; CHECK-LABEL: ham
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define void @ham() {
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bb:
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br label %bb1
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bb1:
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%tmp = phi i64 [ %tmp40, %bb9 ], [ 0, %bb ]
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%tmp2 = phi i32 [ %tmp39, %bb9 ], [ 0, %bb ]
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%tmp3 = icmp sgt i32 undef, 10
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br i1 %tmp3, label %bb2, label %bb3
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bb2:
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%tmp6 = load i32, i32* @global, align 4
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%tmp8 = add nsw i32 %tmp6, %tmp2
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%tmp9 = sext i32 %tmp8 to i64
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br label %bb6
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bb3:
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; CHECK: LBB3_3:
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; CHECK: addq $4, %r
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; CHECK: subl %e
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%tmp14 = phi i64 [ %tmp15, %bb5 ], [ 0, %bb1 ]
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%tmp15 = add nuw i64 %tmp14, 4
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%tmp16 = trunc i64 %tmp14 to i32
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%tmp17 = sub i32 %tmp2, %tmp16
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br label %bb4
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bb4:
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%tmp20 = phi i64 [ %tmp14, %bb3 ], [ %tmp34, %bb5 ]
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%tmp28 = icmp eq i32 %tmp17, 0
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br i1 %tmp28, label %bb5, label %bb8
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bb5:
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%tmp34 = add nuw nsw i64 %tmp20, 1
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%tmp35 = icmp slt i64 %tmp34, %tmp15
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br i1 %tmp35, label %bb4, label %bb3
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bb6:
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store volatile i64 %tmp, i64* @global2, align 8
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store volatile i64 %tmp9, i64* @global2, align 8
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store volatile i32 %tmp6, i32* @global, align 4
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%tmp45 = icmp slt i32 undef, undef
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br i1 %tmp45, label %bb6, label %bb9
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bb8:
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unreachable
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bb9:
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%tmp39 = add nuw nsw i32 %tmp2, 4
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%tmp40 = add nuw i64 %tmp, 4
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br label %bb1
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}
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