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e01dc73ad2
All these headers already depend on CodeGen headers so moving them into CodeGen fixes the layering (since CodeGen depends on Target, not the other way around). llvm-svn: 318490
105 lines
3.2 KiB
C++
105 lines
3.2 KiB
C++
//===- RegisterUsageInfo.cpp - Register Usage Information Storage ---------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// This pass is required to take advantage of the interprocedural register
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/// allocation infrastructure.
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///
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/RegisterUsageInfo.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/Module.h"
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#include "llvm/Pass.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetMachine.h"
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#include <algorithm>
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#include <cassert>
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#include <cstdint>
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#include <utility>
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#include <vector>
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using namespace llvm;
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#define DEBUG_TYPE "ip-regalloc"
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static cl::opt<bool> DumpRegUsage(
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"print-regusage", cl::init(false), cl::Hidden,
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cl::desc("print register usage details collected for analysis."));
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INITIALIZE_PASS(PhysicalRegisterUsageInfo, "reg-usage-info",
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"Register Usage Information Storage", false, true)
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char PhysicalRegisterUsageInfo::ID = 0;
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void PhysicalRegisterUsageInfo::anchor() {}
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bool PhysicalRegisterUsageInfo::doInitialization(Module &M) {
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RegMasks.grow(M.size());
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return false;
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}
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bool PhysicalRegisterUsageInfo::doFinalization(Module &M) {
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if (DumpRegUsage)
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print(errs());
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RegMasks.shrink_and_clear();
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return false;
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}
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void PhysicalRegisterUsageInfo::storeUpdateRegUsageInfo(
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const Function *FP, std::vector<uint32_t> RegMask) {
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assert(FP != nullptr && "Function * can't be nullptr.");
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RegMasks[FP] = std::move(RegMask);
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}
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const std::vector<uint32_t> *
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PhysicalRegisterUsageInfo::getRegUsageInfo(const Function *FP) {
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auto It = RegMasks.find(FP);
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if (It != RegMasks.end())
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return &(It->second);
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return nullptr;
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}
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void PhysicalRegisterUsageInfo::print(raw_ostream &OS, const Module *M) const {
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const TargetRegisterInfo *TRI;
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using FuncPtrRegMaskPair = std::pair<const Function *, std::vector<uint32_t>>;
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SmallVector<const FuncPtrRegMaskPair *, 64> FPRMPairVector;
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// Create a vector of pointer to RegMasks entries
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for (const auto &RegMask : RegMasks)
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FPRMPairVector.push_back(&RegMask);
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// sort the vector to print analysis in alphabatic order of function name.
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std::sort(
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FPRMPairVector.begin(), FPRMPairVector.end(),
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[](const FuncPtrRegMaskPair *A, const FuncPtrRegMaskPair *B) -> bool {
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return A->first->getName() < B->first->getName();
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});
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for (const FuncPtrRegMaskPair *FPRMPair : FPRMPairVector) {
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OS << FPRMPair->first->getName() << " "
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<< "Clobbered Registers: ";
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TRI = TM->getSubtarget<TargetSubtargetInfo>(*(FPRMPair->first))
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.getRegisterInfo();
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for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) {
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if (MachineOperand::clobbersPhysReg(&(FPRMPair->second[0]), PReg))
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OS << TRI->getName(PReg) << " ";
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}
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OS << "\n";
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}
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}
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