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https://github.com/RPCS3/llvm-mirror.git
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8cb4abbc0e
insertp[sd] $0, which is a noop. Before:
_f32: ## @f32
pshufd $1, %xmm1, %xmm2
pshufd $1, %xmm0, %xmm3
addss %xmm2, %xmm3
addss %xmm1, %xmm0
## kill: XMM0<def> XMM0<kill> XMM0<def>
insertps $0, %xmm0, %xmm0
insertps $16, %xmm3, %xmm0
ret
after:
_f32: ## @f32
movdqa %xmm0, %xmm2
addss %xmm1, %xmm2
pshufd $1, %xmm1, %xmm1
pshufd $1, %xmm0, %xmm3
addss %xmm1, %xmm3
movdqa %xmm2, %xmm0
insertps $16, %xmm3, %xmm0
ret
The extra movs are due to a random (poor) scheduling decision.
llvm-svn: 112379
252 lines
7.0 KiB
LLVM
252 lines
7.0 KiB
LLVM
; RUN: llc < %s -mtriple=i686-apple-darwin9 -mattr=sse41 | FileCheck %s -check-prefix=X32
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; RUN: llc < %s -mtriple=x86_64-apple-darwin9 -mattr=sse41 | FileCheck %s -check-prefix=X64
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@g16 = external global i16
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define <4 x i32> @pinsrd_1(i32 %s, <4 x i32> %tmp) nounwind {
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%tmp1 = insertelement <4 x i32> %tmp, i32 %s, i32 1
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ret <4 x i32> %tmp1
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; X32: pinsrd_1:
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; X32: pinsrd $1, 4(%esp), %xmm0
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; X64: pinsrd_1:
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; X64: pinsrd $1, %edi, %xmm0
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}
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define <16 x i8> @pinsrb_1(i8 %s, <16 x i8> %tmp) nounwind {
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%tmp1 = insertelement <16 x i8> %tmp, i8 %s, i32 1
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ret <16 x i8> %tmp1
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; X32: pinsrb_1:
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; X32: pinsrb $1, 4(%esp), %xmm0
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; X64: pinsrb_1:
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; X64: pinsrb $1, %edi, %xmm0
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}
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define <2 x i64> @pmovsxbd_1(i32* %p) nounwind {
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entry:
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%0 = load i32* %p, align 4
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%1 = insertelement <4 x i32> undef, i32 %0, i32 0
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%2 = insertelement <4 x i32> %1, i32 0, i32 1
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%3 = insertelement <4 x i32> %2, i32 0, i32 2
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%4 = insertelement <4 x i32> %3, i32 0, i32 3
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%5 = bitcast <4 x i32> %4 to <16 x i8>
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%6 = tail call <4 x i32> @llvm.x86.sse41.pmovsxbd(<16 x i8> %5) nounwind readnone
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%7 = bitcast <4 x i32> %6 to <2 x i64>
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ret <2 x i64> %7
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; X32: _pmovsxbd_1:
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; X32: movl 4(%esp), %eax
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; X32: pmovsxbd (%eax), %xmm0
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; X64: _pmovsxbd_1:
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; X64: pmovsxbd (%rdi), %xmm0
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}
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define <2 x i64> @pmovsxwd_1(i64* %p) nounwind readonly {
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entry:
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%0 = load i64* %p ; <i64> [#uses=1]
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%tmp2 = insertelement <2 x i64> zeroinitializer, i64 %0, i32 0 ; <<2 x i64>> [#uses=1]
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%1 = bitcast <2 x i64> %tmp2 to <8 x i16> ; <<8 x i16>> [#uses=1]
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%2 = tail call <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16> %1) nounwind readnone ; <<4 x i32>> [#uses=1]
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%3 = bitcast <4 x i32> %2 to <2 x i64> ; <<2 x i64>> [#uses=1]
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ret <2 x i64> %3
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; X32: _pmovsxwd_1:
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; X32: movl 4(%esp), %eax
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; X32: pmovsxwd (%eax), %xmm0
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; X64: _pmovsxwd_1:
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; X64: pmovsxwd (%rdi), %xmm0
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}
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define <2 x i64> @pmovzxbq_1() nounwind {
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entry:
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%0 = load i16* @g16, align 2 ; <i16> [#uses=1]
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%1 = insertelement <8 x i16> undef, i16 %0, i32 0 ; <<8 x i16>> [#uses=1]
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%2 = bitcast <8 x i16> %1 to <16 x i8> ; <<16 x i8>> [#uses=1]
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%3 = tail call <2 x i64> @llvm.x86.sse41.pmovzxbq(<16 x i8> %2) nounwind readnone ; <<2 x i64>> [#uses=1]
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ret <2 x i64> %3
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; X32: _pmovzxbq_1:
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; X32: movl L_g16$non_lazy_ptr, %eax
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; X32: pmovzxbq (%eax), %xmm0
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; X64: _pmovzxbq_1:
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; X64: movq _g16@GOTPCREL(%rip), %rax
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; X64: pmovzxbq (%rax), %xmm0
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}
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declare <4 x i32> @llvm.x86.sse41.pmovsxbd(<16 x i8>) nounwind readnone
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declare <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16>) nounwind readnone
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declare <2 x i64> @llvm.x86.sse41.pmovzxbq(<16 x i8>) nounwind readnone
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define i32 @extractps_1(<4 x float> %v) nounwind {
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%s = extractelement <4 x float> %v, i32 3
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%i = bitcast float %s to i32
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ret i32 %i
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; X32: _extractps_1:
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; X32: extractps $3, %xmm0, %eax
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; X64: _extractps_1:
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; X64: extractps $3, %xmm0, %eax
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}
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define i32 @extractps_2(<4 x float> %v) nounwind {
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%t = bitcast <4 x float> %v to <4 x i32>
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%s = extractelement <4 x i32> %t, i32 3
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ret i32 %s
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; X32: _extractps_2:
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; X32: extractps $3, %xmm0, %eax
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; X64: _extractps_2:
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; X64: extractps $3, %xmm0, %eax
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}
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; The non-store form of extractps puts its result into a GPR.
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; This makes it suitable for an extract from a <4 x float> that
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; is bitcasted to i32, but unsuitable for much of anything else.
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define float @ext_1(<4 x float> %v) nounwind {
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%s = extractelement <4 x float> %v, i32 3
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%t = fadd float %s, 1.0
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ret float %t
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; X32: _ext_1:
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; X32: pshufd $3, %xmm0, %xmm0
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; X32: addss LCPI7_0, %xmm0
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; X64: _ext_1:
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; X64: pshufd $3, %xmm0, %xmm0
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; X64: addss LCPI7_0(%rip), %xmm0
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}
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define float @ext_2(<4 x float> %v) nounwind {
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%s = extractelement <4 x float> %v, i32 3
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ret float %s
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; X32: _ext_2:
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; X32: pshufd $3, %xmm0, %xmm0
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; X64: _ext_2:
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; X64: pshufd $3, %xmm0, %xmm0
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}
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define i32 @ext_3(<4 x i32> %v) nounwind {
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%i = extractelement <4 x i32> %v, i32 3
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ret i32 %i
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; X32: _ext_3:
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; X32: pextrd $3, %xmm0, %eax
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; X64: _ext_3:
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; X64: pextrd $3, %xmm0, %eax
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}
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define <4 x float> @insertps_1(<4 x float> %t1, <4 x float> %t2) nounwind {
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%tmp1 = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %t1, <4 x float> %t2, i32 1) nounwind readnone
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ret <4 x float> %tmp1
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; X32: _insertps_1:
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; X32: insertps $1, %xmm1, %xmm0
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; X64: _insertps_1:
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; X64: insertps $1, %xmm1, %xmm0
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}
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declare <4 x float> @llvm.x86.sse41.insertps(<4 x float>, <4 x float>, i32) nounwind readnone
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define <4 x float> @insertps_2(<4 x float> %t1, float %t2) nounwind {
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%tmp1 = insertelement <4 x float> %t1, float %t2, i32 0
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ret <4 x float> %tmp1
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; X32: _insertps_2:
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; X32: insertps $0, 4(%esp), %xmm0
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; X64: _insertps_2:
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; X64: insertps $0, %xmm1, %xmm0
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}
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define <4 x float> @insertps_3(<4 x float> %t1, <4 x float> %t2) nounwind {
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%tmp2 = extractelement <4 x float> %t2, i32 0
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%tmp1 = insertelement <4 x float> %t1, float %tmp2, i32 0
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ret <4 x float> %tmp1
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; X32: _insertps_3:
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; X32: insertps $0, %xmm1, %xmm0
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; X64: _insertps_3:
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; X64: insertps $0, %xmm1, %xmm0
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}
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define i32 @ptestz_1(<4 x float> %t1, <4 x float> %t2) nounwind {
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%tmp1 = call i32 @llvm.x86.sse41.ptestz(<4 x float> %t1, <4 x float> %t2) nounwind readnone
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ret i32 %tmp1
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; X32: _ptestz_1:
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; X32: ptest %xmm1, %xmm0
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; X32: sete %al
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; X64: _ptestz_1:
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; X64: ptest %xmm1, %xmm0
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; X64: sete %al
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}
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define i32 @ptestz_2(<4 x float> %t1, <4 x float> %t2) nounwind {
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%tmp1 = call i32 @llvm.x86.sse41.ptestc(<4 x float> %t1, <4 x float> %t2) nounwind readnone
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ret i32 %tmp1
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; X32: _ptestz_2:
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; X32: ptest %xmm1, %xmm0
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; X32: setb %al
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; X64: _ptestz_2:
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; X64: ptest %xmm1, %xmm0
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; X64: setb %al
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}
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define i32 @ptestz_3(<4 x float> %t1, <4 x float> %t2) nounwind {
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%tmp1 = call i32 @llvm.x86.sse41.ptestnzc(<4 x float> %t1, <4 x float> %t2) nounwind readnone
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ret i32 %tmp1
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; X32: _ptestz_3:
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; X32: ptest %xmm1, %xmm0
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; X32: seta %al
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; X64: _ptestz_3:
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; X64: ptest %xmm1, %xmm0
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; X64: seta %al
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}
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declare i32 @llvm.x86.sse41.ptestz(<4 x float>, <4 x float>) nounwind readnone
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declare i32 @llvm.x86.sse41.ptestc(<4 x float>, <4 x float>) nounwind readnone
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declare i32 @llvm.x86.sse41.ptestnzc(<4 x float>, <4 x float>) nounwind readnone
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; This used to compile to insertps $0 + insertps $16. insertps $0 is always
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; pointless.
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define <2 x float> @buildvector(<2 x float> %A, <2 x float> %B) nounwind {
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entry:
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%tmp7 = extractelement <2 x float> %A, i32 0
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%tmp5 = extractelement <2 x float> %A, i32 1
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%tmp3 = extractelement <2 x float> %B, i32 0
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%tmp1 = extractelement <2 x float> %B, i32 1
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%add.r = fadd float %tmp7, %tmp3
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%add.i = fadd float %tmp5, %tmp1
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%tmp11 = insertelement <2 x float> undef, float %add.r, i32 0
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%tmp9 = insertelement <2 x float> %tmp11, float %add.i, i32 1
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ret <2 x float> %tmp9
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; X32: buildvector:
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; X32-NOT: insertps $0
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; X32: insertps $16
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; X32-NOT: insertps $0
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; X32: ret
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; X64: buildvector:
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; X64-NOT: insertps $0
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; X64: insertps $16
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; X64-NOT: insertps $0
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; X64: ret
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}
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