1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-25 12:12:47 +01:00
llvm-mirror/test/CodeGen/PowerPC/ppcf128-1-opt.ll
Dan Gohman 5f6f8101d5 Split the Add, Sub, and Mul instruction opcodes into separate
integer and floating-point opcodes, introducing
FAdd, FSub, and FMul.

For now, the AsmParser, BitcodeReader, and IRBuilder all preserve
backwards compatability, and the Core LLVM APIs preserve backwards
compatibility for IR producers. Most front-ends won't need to change
immediately.

This implements the first step of the plan outlined here:
http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt

llvm-svn: 72897
2009-06-04 22:49:04 +00:00

30 lines
801 B
LLVM

; RUN: llvm-as < %s | llc > %t
; ModuleID = '<stdin>'
target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
target triple = "powerpc-apple-darwin8"
define ppc_fp128 @plus(ppc_fp128 %x, ppc_fp128 %y) {
entry:
%tmp3 = fadd ppc_fp128 %x, %y ; <ppc_fp128> [#uses=1]
ret ppc_fp128 %tmp3
}
define ppc_fp128 @minus(ppc_fp128 %x, ppc_fp128 %y) {
entry:
%tmp3 = fsub ppc_fp128 %x, %y ; <ppc_fp128> [#uses=1]
ret ppc_fp128 %tmp3
}
define ppc_fp128 @times(ppc_fp128 %x, ppc_fp128 %y) {
entry:
%tmp3 = fmul ppc_fp128 %x, %y ; <ppc_fp128> [#uses=1]
ret ppc_fp128 %tmp3
}
define ppc_fp128 @divide(ppc_fp128 %x, ppc_fp128 %y) {
entry:
%tmp3 = fdiv ppc_fp128 %x, %y ; <ppc_fp128> [#uses=1]
ret ppc_fp128 %tmp3
}