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10839866a1
This patch implements initial backend support for a -mtune CPU controlled by a "tune-cpu" function attribute. If the attribute is not present X86 will use the resolved CPU from target-cpu attribute or command line. This patch adds MC layer support a tune CPU. Each CPU now has two sets of features stored in their GenSubtargetInfo.inc tables . These features lists are passed separately to the Processor and ProcessorModel classes in tablegen. The tune list defaults to an empty list to avoid changes to non-X86. This annoyingly increases the size of static tables on all target as we now store 24 more bytes per CPU. I haven't quantified the overall impact, but I can if we're concerned. One new test is added to X86 to show a few tuning features with mismatched tune-cpu and target-cpu/target-feature attributes to demonstrate independent control. Another new test is added to demonstrate that the scheduler model follows the tune CPU. I have not added a -mtune to llc/opt or MC layer command line yet. With no attributes we'll just use the -mcpu for both. MC layer tools will always follow the normal CPU for tuning. Differential Revision: https://reviews.llvm.org/D85165
62 lines
2.2 KiB
C++
62 lines
2.2 KiB
C++
//===-- WebAssemblySubtarget.cpp - WebAssembly Subtarget Information ------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file implements the WebAssembly-specific subclass of
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/// TargetSubtarget.
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///
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//===----------------------------------------------------------------------===//
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#include "WebAssemblySubtarget.h"
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#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
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#include "WebAssemblyInstrInfo.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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#define DEBUG_TYPE "wasm-subtarget"
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#define GET_SUBTARGETINFO_CTOR
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#define GET_SUBTARGETINFO_TARGET_DESC
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#include "WebAssemblyGenSubtargetInfo.inc"
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WebAssemblySubtarget &
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WebAssemblySubtarget::initializeSubtargetDependencies(StringRef CPU,
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StringRef FS) {
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// Determine default and user-specified characteristics
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LLVM_DEBUG(llvm::dbgs() << "initializeSubtargetDependencies\n");
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if (CPU.empty())
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CPU = "generic";
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ParseSubtargetFeatures(CPU, /*TuneCPU*/ CPU, FS);
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return *this;
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}
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WebAssemblySubtarget::WebAssemblySubtarget(const Triple &TT,
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const std::string &CPU,
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const std::string &FS,
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const TargetMachine &TM)
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: WebAssemblyGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
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TargetTriple(TT), FrameLowering(),
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InstrInfo(initializeSubtargetDependencies(CPU, FS)), TSInfo(),
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TLInfo(TM, *this) {}
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bool WebAssemblySubtarget::enableAtomicExpand() const {
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// If atomics are disabled, atomic ops are lowered instead of expanded
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return hasAtomics();
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}
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bool WebAssemblySubtarget::enableMachineScheduler() const {
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// Disable the MachineScheduler for now. Even with ShouldTrackPressure set and
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// enableMachineSchedDefaultSched overridden, it appears to have an overall
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// negative effect for the kinds of register optimizations we're doing.
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return false;
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}
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bool WebAssemblySubtarget::useAA() const { return true; }
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