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llvm-mirror/test/CodeGen/RISCV
Alex Bradbury 132ad3d36c [RISCV] Reserve an emergency spill slot for the register scavenger when necessary
Although the register scavenger can often find a spare register, an emergency 
spill slot is needed to guarantee success. Reserve this slot in cases where 
the function is known to have a large stack (meaning the scavenger may be 
needed when forming stack addresses).

llvm-svn: 322269
2018-01-11 11:17:19 +00:00
..
addc-adde-sube-subc.ll
alloca.ll
alu32.ll
analyze-branch.ll [RISCV] Implement support for the BranchRelaxation pass 2018-01-10 21:05:07 +00:00
bare-select.ll
blockaddress.ll
branch-relaxation.ll [RISCV] Implement support for the BranchRelaxation pass 2018-01-10 21:05:07 +00:00
branch.ll [RISCV] Implement branch analysis 2018-01-10 20:47:00 +00:00
bswap-ctlz-cttz-ctpop.ll [RISCV] Implement support for the BranchRelaxation pass 2018-01-10 21:05:07 +00:00
byval.ll
calling-conv-sext-zext.ll
calling-conv.ll
calls.ll
div.ll
fp128.ll
frame.ll
frameaddr-returnaddr.ll [RISCV] Add support for llvm.{frameaddress,returnaddress} intrinsics 2018-01-10 20:12:00 +00:00
i32-icmp.ll
imm.ll
indirectbr.ll
inline-asm.ll [RISCV] Add basic support for inline asm constraints 2018-01-10 20:05:09 +00:00
jumptable.ll [RISCV] Implement support for the BranchRelaxation pass 2018-01-10 21:05:07 +00:00
large-stack.ll [RISCV] Reserve an emergency spill slot for the register scavenger when necessary 2018-01-11 11:17:19 +00:00
lit.local.cfg
mem.ll
mul.ll
rem.ll
rotl-rotr.ll
select-cc.ll [RISCV] Implement branch analysis 2018-01-10 20:47:00 +00:00
sext-zext-trunc.ll
shifts.ll
vararg.ll
wide-mem.ll