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llvm-mirror/test/CodeGen/AArch64/GlobalISel/select-trunc.mir
Amara Emerson d788c9df62 [AArch64][GlobalISel] Add support for s128 loads, stores, extracts, truncs.
We need to be able to load and store s128 for memcpy inlining, where we want to
generate Q register mem ops. Making these legal also requires that we add some
support in other instructions. Regbankselect should also know about these since
they have no GPR register class that can hold them, so need special handling to
live on the FPR bank.

Differential Revision: https://reviews.llvm.org/D65166

llvm-svn: 366857
2019-07-23 22:05:13 +00:00

124 lines
2.7 KiB
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
--- |
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
define void @trunc_s32_s64() { ret void }
define void @trunc_s8_s64() { ret void }
define void @trunc_s1_s32() { ret void }
define void @trunc_s64_s128() { ret void }
define void @trunc_s32_s128() { ret void }
...
---
name: trunc_s32_s64
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: trunc_s32_s64
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:gpr32sp = COPY [[COPY]].sub_32
; CHECK: $w0 = COPY [[COPY1]]
%0(s64) = COPY $x0
%1(s32) = G_TRUNC %0
$w0 = COPY %1(s32)
...
---
name: trunc_s8_s64
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: trunc_s8_s64
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]].sub_32
; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[COPY1]]
; CHECK: $w0 = COPY [[COPY2]]
%0(s64) = COPY $x0
%1(s8) = G_TRUNC %0
%2:gpr(s32) = G_ANYEXT %1
$w0 = COPY %2(s32)
...
---
name: trunc_s1_s32
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
body: |
bb.0:
liveins: $w0
; CHECK-LABEL: name: trunc_s1_s32
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[COPY]]
; CHECK: $w0 = COPY [[COPY1]]
%0(s32) = COPY $w0
%1(s1) = G_TRUNC %0
%2:gpr(s32) = G_ANYEXT %1
$w0 = COPY %2(s32)
...
---
name: trunc_s64_s128
legalized: true
regBankSelected: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: trunc_s64_s128
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]].dsub
; CHECK: $x0 = COPY [[COPY1]]
%0(s128) = COPY $q0
%1(s64) = G_TRUNC %0
$x0 = COPY %1(s64)
...
---
name: trunc_s32_s128
legalized: true
regBankSelected: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: trunc_s32_s128
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY [[COPY]].ssub
; CHECK: $w0 = COPY [[COPY1]]
%0(s128) = COPY $q0
%1(s32) = G_TRUNC %0
$w0 = COPY %1(s32)
...