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We need to be able to load and store s128 for memcpy inlining, where we want to generate Q register mem ops. Making these legal also requires that we add some support in other instructions. Regbankselect should also know about these since they have no GPR register class that can hold them, so need special handling to live on the FPR bank. Differential Revision: https://reviews.llvm.org/D65166 llvm-svn: 366857
124 lines
2.7 KiB
YAML
124 lines
2.7 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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--- |
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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define void @trunc_s32_s64() { ret void }
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define void @trunc_s8_s64() { ret void }
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define void @trunc_s1_s32() { ret void }
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define void @trunc_s64_s128() { ret void }
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define void @trunc_s32_s128() { ret void }
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...
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---
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name: trunc_s32_s64
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: trunc_s32_s64
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[COPY1:%[0-9]+]]:gpr32sp = COPY [[COPY]].sub_32
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; CHECK: $w0 = COPY [[COPY1]]
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%0(s64) = COPY $x0
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%1(s32) = G_TRUNC %0
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$w0 = COPY %1(s32)
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...
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---
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name: trunc_s8_s64
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: trunc_s8_s64
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; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
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; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]].sub_32
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; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[COPY1]]
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; CHECK: $w0 = COPY [[COPY2]]
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%0(s64) = COPY $x0
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%1(s8) = G_TRUNC %0
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%2:gpr(s32) = G_ANYEXT %1
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$w0 = COPY %2(s32)
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...
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---
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name: trunc_s1_s32
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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body: |
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bb.0:
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liveins: $w0
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; CHECK-LABEL: name: trunc_s1_s32
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[COPY]]
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; CHECK: $w0 = COPY [[COPY1]]
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%0(s32) = COPY $w0
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%1(s1) = G_TRUNC %0
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%2:gpr(s32) = G_ANYEXT %1
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$w0 = COPY %2(s32)
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...
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---
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name: trunc_s64_s128
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: trunc_s64_s128
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; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]].dsub
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; CHECK: $x0 = COPY [[COPY1]]
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%0(s128) = COPY $q0
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%1(s64) = G_TRUNC %0
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$x0 = COPY %1(s64)
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...
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---
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name: trunc_s32_s128
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: trunc_s32_s128
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; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY [[COPY]].ssub
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; CHECK: $w0 = COPY [[COPY1]]
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%0(s128) = COPY $q0
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%1(s32) = G_TRUNC %0
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$w0 = COPY %1(s32)
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...
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