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1bb14916f2
This is the main CodeGen patch to support the arm64_32 watchOS ABI in LLVM. FastISel is mostly disabled for now since it would generate incorrect code for ILP32. llvm-svn: 371722
57 lines
1.4 KiB
LLVM
57 lines
1.4 KiB
LLVM
; RUN: llc -mtriple=arm64_32-apple-ios %s -o - | FileCheck %s
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define void @test_va_copy(i8* %dst, i8* %src) {
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; CHECK-LABEL: test_va_copy:
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; CHECK: ldr [[PTR:w[0-9]+]], [x1]
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; CHECK: str [[PTR]], [x0]
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call void @llvm.va_copy(i8* %dst, i8* %src)
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ret void
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}
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define void @test_va_start(i32, ...) {
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; CHECK-LABEL: test_va_start
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; CHECK: add x[[LIST:[0-9]+]], sp, #16
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; CHECK: str w[[LIST]],
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%slot = alloca i8*, align 4
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%list = bitcast i8** %slot to i8*
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call void @llvm.va_start(i8* %list)
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ret void
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}
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define void @test_va_start_odd([8 x i64], i32, ...) {
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; CHECK-LABEL: test_va_start_odd:
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; CHECK: add x[[LIST:[0-9]+]], sp, #20
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; CHECK: str w[[LIST]],
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%slot = alloca i8*, align 4
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%list = bitcast i8** %slot to i8*
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call void @llvm.va_start(i8* %list)
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ret void
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}
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define i8* @test_va_arg(i8** %list) {
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; CHECK-LABEL: test_va_arg:
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; CHECK: ldr w[[LOC:[0-9]+]], [x0]
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; CHECK: add [[NEXTLOC:w[0-9]+]], w[[LOC]], #4
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; CHECK: str [[NEXTLOC]], [x0]
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; CHECK: ldr w0, [x[[LOC]]]
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%res = va_arg i8** %list, i8*
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ret i8* %res
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}
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define i8* @really_test_va_arg(i8** %list, i1 %tst) {
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; CHECK-LABEL: really_test_va_arg:
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; CHECK: ldr w[[LOC:[0-9]+]], [x0]
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; CHECK: add [[NEXTLOC:w[0-9]+]], w[[LOC]], #4
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; CHECK: str [[NEXTLOC]], [x0]
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; CHECK: ldr w[[VAARG:[0-9]+]], [x[[LOC]]]
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; CHECK: csel x0, x[[VAARG]], xzr
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%tmp = va_arg i8** %list, i8*
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%res = select i1 %tst, i8* %tmp, i8* null
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ret i8* %res
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}
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declare void @llvm.va_start(i8*)
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declare void @llvm.va_copy(i8*, i8*)
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