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60f7be42e3
For `MC_GlobalAddress` operands referencing **certain** GlobalObjects, we can lower them to STB_LOCAL aliases to avoid costs brought by assembler/linker's conservative decisions about symbol interposition: * An assembler conservatively assumes a global default visibility symbol interposable (ELF semantics). So relocations in object files are needed even if the code generator assumed the definition exact and non-interposable. * The relocations can cause the creation of PLT entries on some targets for -shared links. A linker conservatively assumes a global default visibility symbol interposable (if not otherwise constrained by -Bsymbolic/--dynamic-list/VER_NDX_LOCAL/etc). "certain" refers to GlobalObjects in the intersection of `hasExactDefinition() and !isInterposable()`: `external`, `appending`, `internal`, `private`. Local linkages (`internal` and `private`) cannot be interposed. `appending` is for very few objects LLVM interpret specially. So the set just includes `external`. This patch emits STB_LOCAL aliases (.Lfoo$local) for such GlobalObjects, so that targets can lower MC_GlobalAddress operands to STB_LOCAL aliases if applicable. We may extend the scope and include GlobalAlias in the future. LLVM's existing -fno-semantic-interposition behaviors give us license to do such optimizations: * Various optimizations (ipconstprop, inliner, sccp, sroa, etc) treat normal ExternalLinkage GlobalObjects as non-interposable. * Before D72197, MC resolved a PC-relative VK_None fixup to a non-local symbol at assembly time (no outstanding relocation), if the target is defined in the same section. Put it simply, even if IR optimizations failed to optimize and allowed interposition for the function call in `void foo() {} void bar() { foo(); }`, the assembler would disallow it. This patch sets up AsmPrinter infrastructure to make -fno-semantic-interposition more so. With and without the patch, the object file output should be identical: `.Lfoo$local` does not take a symbol table entry. Reviewed By: sfertile Differential Revision: https://reviews.llvm.org/D73228
218 lines
5.8 KiB
LLVM
218 lines
5.8 KiB
LLVM
; RUN: llc -emulated-tls -mtriple=aarch64-linux-android \
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; RUN: -relocation-model=pic -frame-pointer=all < %s | FileCheck -check-prefix=ARM64 %s
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; RUN: llc -mtriple=aarch64-linux-android \
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; RUN: -relocation-model=pic -frame-pointer=all < %s | FileCheck -check-prefix=ARM64 %s
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; Copied from X86/emutls.ll
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; Use my_emutls_get_address like __emutls_get_address.
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@my_emutls_v_xyz = external global i8*, align 4
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declare i8* @my_emutls_get_address(i8*)
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define i32 @my_get_xyz() {
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; ARM64-LABEL: my_get_xyz:
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; ARM64: adrp x0, :got:my_emutls_v_xyz
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; ARM64-NEXT: ldr x0, [x0, :got_lo12:my_emutls_v_xyz]
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; ARM64-NEXT: bl my_emutls_get_address
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; ARM64-NEXT: ldr w0, [x0]
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; ARM64-NEXT: ldp x29, x30, [sp]
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entry:
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%call = call i8* @my_emutls_get_address(i8* bitcast (i8** @my_emutls_v_xyz to i8*))
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%0 = bitcast i8* %call to i32*
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%1 = load i32, i32* %0, align 4
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ret i32 %1
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}
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@i1 = thread_local global i32 15
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@i2 = external thread_local global i32
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@i3 = internal thread_local global i32 15
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@i4 = hidden thread_local global i32 15
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@i5 = external hidden thread_local global i32
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@s1 = thread_local global i16 15
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@b1 = thread_local global i8 0
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define i32 @f1() {
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; ARM64-LABEL: f1:
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; ARM64: adrp x0, :got:__emutls_v.i1
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; ARM64-NEXT: ldr x0, [x0, :got_lo12:__emutls_v.i1]
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; ARM64-NEXT: bl __emutls_get_address
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; ARM64-NEXT: ldr w0, [x0]
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; ARM64-NEXT: ldp x29, x30, [sp]
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entry:
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%tmp1 = load i32, i32* @i1
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ret i32 %tmp1
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}
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define i32* @f2() {
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; ARM64-LABEL: f2:
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; ARM64: adrp x0, :got:__emutls_v.i1
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; ARM64-NEXT: ldr x0, [x0, :got_lo12:__emutls_v.i1]
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; ARM64-NEXT: bl __emutls_get_address
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; ARM64-NEXT: ldp x29, x30, [sp]
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entry:
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ret i32* @i1
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}
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define i32 @f5() nounwind {
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; ARM64-LABEL: f5:
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; ARM64: adrp x0, __emutls_v.i3
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; ARM64: add x0, x0, :lo12:__emutls_v.i3
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; ARM64: bl __emutls_get_address
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; ARM64-NEXT: ldr w0, [x0]
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entry:
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%tmp1 = load i32, i32* @i3
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ret i32 %tmp1
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}
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define i32* @f6() {
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; ARM64-LABEL: f6:
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; ARM64: adrp x0, __emutls_v.i3
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; ARM64: add x0, x0, :lo12:__emutls_v.i3
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; ARM64-NEXT: bl __emutls_get_address
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; ARM64-NEXT: ldp x29, x30, [sp]
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entry:
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ret i32* @i3
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}
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; Simple test of comdat __thread variables.
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; template <class T> struct A { static __thread T x; };
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; template <class T> T __thread A<T>::x;
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; int getIntX() { return A<int>::x++; }
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; float getFloatX() { return A<float>::x++; }
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$_ZN1AIiE1xE = comdat any
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$_ZN1AIfE1xE = comdat any
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@_ZN1AIiE1xE = linkonce_odr thread_local global i32 0, comdat, align 4
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@_ZN1AIfE1xE = linkonce_odr thread_local global float 0.000000e+00, comdat, align 4
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define i32 @_Z7getIntXv() {
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; ARM64-LABEL: _Z7getIntXv:
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; ARM64: adrp x0, :got:__emutls_v._ZN1AIiE1xE
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; ARM64: ldr x0, [x0, :got_lo12:__emutls_v._ZN1AIiE1xE]
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; ARM64-NEXT: bl __emutls_get_address
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; ARM64-NEXT: ldr {{.*}}, [x0]
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; ARM64: add
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; ARM64: str {{.*}}, [x0]
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entry:
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%0 = load i32, i32* @_ZN1AIiE1xE, align 4
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%inc = add nsw i32 %0, 1
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store i32 %inc, i32* @_ZN1AIiE1xE, align 4
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ret i32 %0
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}
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define float @_Z9getFloatXv() {
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; ARM64-LABEL: _Z9getFloatXv:
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; ARM64: adrp x0, :got:__emutls_v._ZN1AIfE1xE
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; ARM64: ldr x0, [x0, :got_lo12:__emutls_v._ZN1AIfE1xE]
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; ARM64-NEXT: bl __emutls_get_address
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; ARM64-NEXT: ldr {{.*}}, [x0]
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; ARM64: fadd s{{.*}}, s
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; ARM64: str s{{.*}}, [x0]
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entry:
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%0 = load float, float* @_ZN1AIfE1xE, align 4
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%inc = fadd float %0, 1.000000e+00
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store float %inc, float* @_ZN1AIfE1xE, align 4
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ret float %0
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}
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;;;;;;;;;;;;;; 64-bit __emutls_v. and __emutls_t.
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; ARM64: .data{{$}}
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; ARM64: .globl __emutls_v.i1
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; ARM64-LABEL: __emutls_v.i1:
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; ARM64-NEXT: .xword 4
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; ARM64-NEXT: .xword 4
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; ARM64-NEXT: .xword 0
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; ARM64-NEXT: .xword __emutls_t.i1
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; ARM64: .section .rodata,
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; ARM64-LABEL: __emutls_t.i1:
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; ARM64-NEXT: .word 15
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; ARM64-NOT: __emutls_v.i2
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; ARM64: .data{{$}}
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; ARM64-NOT: .globl
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; ARM64-LABEL: __emutls_v.i3:
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; ARM64-NEXT: .xword 4
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; ARM64-NEXT: .xword 4
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; ARM64-NEXT: .xword 0
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; ARM64-NEXT: .xword __emutls_t.i3
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; ARM64: .section .rodata,
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; ARM64-LABEL: __emutls_t.i3:
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; ARM64-NEXT: .word 15
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; ARM64: .hidden __emutls_v.i4
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; ARM64: .data{{$}}
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; ARM64: .globl __emutls_v.i4
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; ARM64-LABEL: __emutls_v.i4:
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; ARM64-NEXT: .L__emutls_v.i4$local:
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; ARM64-NEXT: .xword 4
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; ARM64-NEXT: .xword 4
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; ARM64-NEXT: .xword 0
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; ARM64-NEXT: .xword __emutls_t.i4
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; ARM64: .section .rodata,
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; ARM64-LABEL: __emutls_t.i4:
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; ARM64-NEXT: .L__emutls_t.i4$local:
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; ARM64-NEXT: .word 15
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; ARM64-NOT: __emutls_v.i5:
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; ARM64: .hidden __emutls_v.i5
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; ARM64-NOT: __emutls_v.i5:
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; ARM64: .data{{$}}
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; ARM64: .globl __emutls_v.s1
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; ARM64-LABEL: __emutls_v.s1:
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; ARM64-NEXT: .xword 2
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; ARM64-NEXT: .xword 2
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; ARM64-NEXT: .xword 0
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; ARM64-NEXT: .xword __emutls_t.s1
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; ARM64: .section .rodata,
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; ARM64-LABEL: __emutls_t.s1:
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; ARM64-NEXT: .hword 15
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; ARM64: .data{{$}}
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; ARM64-LABEL: __emutls_v.b1:
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; ARM64-NEXT: .xword 1
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; ARM64-NEXT: .xword 1
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; ARM64-NEXT: .xword 0
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; ARM64-NEXT: .xword 0
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; ARM64-NOT: __emutls_t.b1
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; ARM64: .section .data.__emutls_v._ZN1AIiE1xE,{{.*}},__emutls_v._ZN1AIiE1xE,comdat
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; ARM64: .weak __emutls_v._ZN1AIiE1xE
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; ARM64: .p2align 3
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; ARM64-LABEL: __emutls_v._ZN1AIiE1xE:
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; ARM64-NEXT: .xword 4
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; ARM64-NEXT: .xword 4
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; ARM64-NEXT: .xword 0
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; ARM64-NEXT: .xword 0
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; ARM64: .section .data.__emutls_v._ZN1AIfE1xE,{{.*}},__emutls_v._ZN1AIfE1xE,comdat
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; ARM64: .weak __emutls_v._ZN1AIfE1xE
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; ARM64: .p2align 3
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; ARM64-LABEL: __emutls_v._ZN1AIfE1xE:
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; ARM64-NEXT: .xword 4
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; ARM64-NEXT: .xword 4
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; ARM64-NEXT: .xword 0
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; ARM64-NEXT: .xword __emutls_t._ZN1AIfE1xE
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; ARM64: .section .rodata.__emutls_t._ZN1AIfE1xE,{{.*}},__emutls_t._ZN1AIfE1xE,comdat
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; ARM64: .weak __emutls_t._ZN1AIfE1xE
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; ARM64: .p2align 2
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; ARM64-LABEL: __emutls_t._ZN1AIfE1xE:
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; ARM64-NEXT: .word 0
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; ARM64-NEXT: .size
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