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ea5a6285ae
This is generally more readable due to the way the assembler aliases work. (This causes a lot of test changes, but it's not really as scary as it looks at first glance; it's just mechanically changing a bunch of checks for orr to check for mov instead.) Differential Revision: https://reviews.llvm.org/D59720 llvm-svn: 356954
51 lines
1.6 KiB
LLVM
51 lines
1.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64 < %s | FileCheck %s
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; This should codegen to fmaxnm with no-signed-zeros.
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define float @fmaxnm(i32 %i1, i32 %i2) #0 {
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; CHECK-LABEL: fmaxnm:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ucvtf s0, w0
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; CHECK-NEXT: fmov s1, #11.00000000
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; CHECK-NEXT: ucvtf s2, w1
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; CHECK-NEXT: fmov s3, #17.00000000
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; CHECK-NEXT: fadd s0, s0, s1
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; CHECK-NEXT: fadd s1, s2, s3
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; CHECK-NEXT: fcmp s0, s1
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; CHECK-NEXT: fcsel s0, s0, s1, pl
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; CHECK-NEXT: ret
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%f1 = uitofp i32 %i1 to float
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%fadd1 = fadd float %f1, 11.0
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%f2 = uitofp i32 %i2 to float
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%fadd2 = fadd float %f2, 17.0
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%cmp = fcmp uge float %fadd1, %fadd2
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%val = select i1 %cmp, float %fadd1, float %fadd2
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ret float %val
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}
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; If f1 is 0, fmul is NaN because 0.0 * -INF = NaN
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; Therefore, this is not fmaxnm.
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define float @not_fmaxnm_maybe_nan(i32 %i1, i32 %i2) #0 {
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; CHECK-LABEL: not_fmaxnm_maybe_nan:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #-8388608
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; CHECK-NEXT: ucvtf s0, w0
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; CHECK-NEXT: ucvtf s1, w1
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; CHECK-NEXT: fmov s2, #17.00000000
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; CHECK-NEXT: fmov s3, w8
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; CHECK-NEXT: fmul s0, s0, s3
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; CHECK-NEXT: fadd s1, s1, s2
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; CHECK-NEXT: fcmp s0, s1
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; CHECK-NEXT: fcsel s0, s0, s1, pl
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; CHECK-NEXT: ret
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%f1 = uitofp i32 %i1 to float
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%fmul = fmul float %f1, 0xfff0000000000000 ; -INFINITY as 64-bit hex
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%f2 = uitofp i32 %i2 to float
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%fadd2 = fadd float %f2, 17.0
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%cmp = fcmp uge float %fmul, %fadd2
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%val = select i1 %cmp, float %fmul, float %fadd2
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ret float %val
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}
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attributes #0 = { "no-signed-zeros-fp-math"="true" }
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