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23 lines
1.0 KiB
LLVM
23 lines
1.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -o - %s -mtriple aarch64-- -mattr +slow-misaligned-128store | FileCheck %s
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; Checks for a bug where selection dag store merging would construct wrong
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; indices when extracting values from vectors, resulting in an invalid
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; lane duplication in this case.
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; The only way I could trigger stores with mismatching types getting merged was
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; via the aarch64 slow-misaligned-128store code splitting stores earlier.
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; aarch64 feature slow-misaligned-128store splits the following store.
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; store merging immediately merges it back together (but used to get the
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; merging wrong), this is the only way I was able to reproduce the bug...
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define void @func(<2 x double>* %sptr, <2 x double>* %dptr) {
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; CHECK-LABEL: func:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: str q0, [x1]
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; CHECK-NEXT: ret
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%load = load <2 x double>, <2 x double>* %sptr, align 8
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store <2 x double> %load, <2 x double>* %dptr, align 4
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ret void
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}
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