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01d632b33a
Summary:
The following intrinsics are added:
* @llvm.aarch64.sve.ldff1.gather
* @llvm.aarch64.sve.ldff1.gather.index
* @llvm.aarch64.sve.ldff1.gather_sxtw
* @llvm.aarch64.sve.ldff1.gather.uxtw
* @llvm.aarch64.sve.ldff1.gather_sxtw.index
* @llvm.aarch64.sve.ldff1.gather.uxtw.index
* @llvm.aarch64.sve.ldff1.gather.scalar.offset
Although this patch is quite substantial, the vast majority of the
implementation is just a 'copy & paste' of the implementation of regular
gather loads, including tests. There's only a handful of new
definitions:
* AArch64ISD nodes defined in AArch64ISelLowering.h (e.g. GLDFF1)
* Seleciton DAG Types in AArch64SVEInstrInfo.td (e.g.
AArch64ldff1_gather)
* intrinsics in IntrinsicsAArch64.td (e.g. aarch64_sve_ldff1_gather)
* Pseudo instructions in SVEInstrFormats.td to workaround the issue of
use-before-def for the FFR register.
Reviewed By: sdesmalen
Differential Revision: https://reviews.llvm.org/D75128
187 lines
10 KiB
LLVM
187 lines
10 KiB
LLVM
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
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;
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; LDFF1B, LDFF1W, LDFF1H, LDFF1D: vector base + scalar offset (index)
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; e.g. ldff1b { z0.d }, p0/z, [x0, z0.d]
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;
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; LDFF1B
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define <vscale x 4 x i32> @gldff1b_s_scalar_offset(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %base, i64 %offset) {
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; CHECK-LABEL: gldff1b_s_scalar_offset:
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; CHECK: ldff1b { z0.s }, p0/z, [x0, z0.s, uxtw]
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; CHECK-NEXT: ret
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%load = call <vscale x 4 x i8> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i8.nxv4i32(<vscale x 4 x i1> %pg,
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<vscale x 4 x i32> %base,
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i64 %offset)
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%res = zext <vscale x 4 x i8> %load to <vscale x 4 x i32>
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 2 x i64> @gldff1b_d_scalar_offset(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %base, i64 %offset) {
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; CHECK-LABEL: gldff1b_d_scalar_offset:
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; CHECK: ldff1b { z0.d }, p0/z, [x0, z0.d]
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; CHECK-NEXT: ret
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%load = call <vscale x 2 x i8> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i8.nxv2i64(<vscale x 2 x i1> %pg,
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<vscale x 2 x i64> %base,
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i64 %offset)
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%res = zext <vscale x 2 x i8> %load to <vscale x 2 x i64>
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ret <vscale x 2 x i64> %res
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}
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; LDFF1H
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define <vscale x 4 x i32> @gldff1h_s_scalar_offset(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %base, i64 %offset) {
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; CHECK-LABEL: gldff1h_s_scalar_offset:
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; CHECK: ldff1h { z0.s }, p0/z, [x0, z0.s, uxtw]
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; CHECK-NEXT: ret
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%load = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i1> %pg,
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<vscale x 4 x i32> %base,
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i64 %offset)
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%res = zext <vscale x 4 x i16> %load to <vscale x 4 x i32>
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 2 x i64> @gldff1h_d_scalar_offset(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %base, i64 %offset) {
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; CHECK-LABEL: gldff1h_d_scalar_offset:
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; CHECK: ldff1h { z0.d }, p0/z, [x0, z0.d]
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; CHECK-NEXT: ret
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%load = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64(<vscale x 2 x i1> %pg,
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<vscale x 2 x i64> %base,
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i64 %offset)
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%res = zext <vscale x 2 x i16> %load to <vscale x 2 x i64>
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ret <vscale x 2 x i64> %res
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}
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; LDFF1W
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define <vscale x 4 x i32> @gldff1w_s_scalar_offset(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %base, i64 %offset) {
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; CHECK-LABEL: gldff1w_s_scalar_offset:
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; CHECK: ldff1w { z0.s }, p0/z, [x0, z0.s, uxtw]
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; CHECK-NEXT: ret
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%load = call <vscale x 4 x i32> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i32.nxv4i32(<vscale x 4 x i1> %pg,
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<vscale x 4 x i32> %base,
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i64 %offset)
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ret <vscale x 4 x i32> %load
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}
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define <vscale x 2 x i64> @gldff1w_d_scalar_offset(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %base, i64 %offset) {
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; CHECK-LABEL: gldff1w_d_scalar_offset:
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; CHECK: ldff1w { z0.d }, p0/z, [x0, z0.d]
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; CHECK-NEXT: ret
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%load = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1> %pg,
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<vscale x 2 x i64> %base,
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i64 %offset)
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%res = zext <vscale x 2 x i32> %load to <vscale x 2 x i64>
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ret <vscale x 2 x i64> %res
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}
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define <vscale x 4 x float> @gldff1w_s_scalar_offset_float(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %base, i64 %offset) {
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; CHECK-LABEL: gldff1w_s_scalar_offset_float:
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; CHECK: ldff1w { z0.s }, p0/z, [x0, z0.s, uxtw]
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; CHECK-NEXT: ret
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%load = call <vscale x 4 x float> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4f32.nxv4i32(<vscale x 4 x i1> %pg,
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<vscale x 4 x i32> %base,
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i64 %offset)
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ret <vscale x 4 x float> %load
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}
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; LDFF1D
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define <vscale x 2 x i64> @gldff1d_d_scalar_offset(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %base, i64 %offset) {
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; CHECK-LABEL: gldff1d_d_scalar_offset:
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; CHECK: ldff1d { z0.d }, p0/z, [x0, z0.d]
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; CHECK-NEXT: ret
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%load = call <vscale x 2 x i64> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i64.nxv2i64(<vscale x 2 x i1> %pg,
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<vscale x 2 x i64> %base,
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i64 %offset)
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ret <vscale x 2 x i64> %load
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}
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define <vscale x 2 x double> @gldff1d_d_scalar_offset_double(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %base, i64 %offset) {
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; CHECK-LABEL: gldff1d_d_scalar_offset_double:
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; CHECK: ldff1d { z0.d }, p0/z, [x0, z0.d]
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; CHECK-NEXT: ret
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%load = call <vscale x 2 x double> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2f64.nxv2i64(<vscale x 2 x i1> %pg,
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<vscale x 2 x i64> %base,
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i64 %offset)
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ret <vscale x 2 x double> %load
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}
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; LDFF1SB, LDFF1SW, LDFF1SH: vector base + scalar offset (index)
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; e.g. ldff1b { z0.d }, p0/z, [x0, z0.d]
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;
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; LDFF1SB
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define <vscale x 4 x i32> @gldff1sb_s_scalar_offset(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %base, i64 %offset) {
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; CHECK-LABEL: gldff1sb_s_scalar_offset:
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; CHECK: ldff1sb { z0.s }, p0/z, [x0, z0.s, uxtw]
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; CHECK-NEXT: ret
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%load = call <vscale x 4 x i8> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i8.nxv4i32(<vscale x 4 x i1> %pg,
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<vscale x 4 x i32> %base,
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i64 %offset)
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%res = sext <vscale x 4 x i8> %load to <vscale x 4 x i32>
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 2 x i64> @gldff1sb_d_scalar_offset(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %base, i64 %offset) {
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; CHECK-LABEL: gldff1sb_d_scalar_offset:
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; CHECK: ldff1sb { z0.d }, p0/z, [x0, z0.d]
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; CHECK-NEXT: ret
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%load = call <vscale x 2 x i8> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i8.nxv2i64(<vscale x 2 x i1> %pg,
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<vscale x 2 x i64> %base,
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i64 %offset)
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%res = sext <vscale x 2 x i8> %load to <vscale x 2 x i64>
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ret <vscale x 2 x i64> %res
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}
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; LDFF1SH
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define <vscale x 4 x i32> @gldff1sh_s_scalar_offset(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %base, i64 %offset) {
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; CHECK-LABEL: gldff1sh_s_scalar_offset:
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; CHECK: ldff1sh { z0.s }, p0/z, [x0, z0.s, uxtw]
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; CHECK-NEXT: ret
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%load = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i1> %pg,
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<vscale x 4 x i32> %base,
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i64 %offset)
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%res = sext <vscale x 4 x i16> %load to <vscale x 4 x i32>
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 2 x i64> @gldff1sh_d_scalar_offset(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %base, i64 %offset) {
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; CHECK-LABEL: gldff1sh_d_scalar_offset:
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; CHECK: ldff1sh { z0.d }, p0/z, [x0, z0.d]
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; CHECK-NEXT: ret
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%load = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64(<vscale x 2 x i1> %pg,
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<vscale x 2 x i64> %base,
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i64 %offset)
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%res = sext <vscale x 2 x i16> %load to <vscale x 2 x i64>
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ret <vscale x 2 x i64> %res
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}
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; LDFF1SW
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define <vscale x 2 x i64> @gldff1sw_d_scalar_offset(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %base, i64 %offset) {
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; CHECK-LABEL: gldff1sw_d_scalar_offset:
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; CHECK: ldff1sw { z0.d }, p0/z, [x0, z0.d]
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; CHECK-NEXT: ret
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%load = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1> %pg,
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<vscale x 2 x i64> %base,
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i64 %offset)
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%res = sext <vscale x 2 x i32> %load to <vscale x 2 x i64>
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ret <vscale x 2 x i64> %res
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}
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; LDFF1B/LDFF1SB
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declare <vscale x 4 x i8> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i8.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i64)
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declare <vscale x 2 x i8> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i8.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64)
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; LDFF1H/LDFF1SH
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declare <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i64)
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declare <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64)
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; LDFF1W/LDFF1SW
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declare <vscale x 4 x i32> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i32.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i64)
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declare <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64)
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declare <vscale x 4 x float> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4f32.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i64)
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; LDFF1D
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declare <vscale x 2 x i64> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i64.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64)
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declare <vscale x 2 x double> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2f64.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64)
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