mirror of
https://github.com/RPCS3/llvm-mirror.git
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75e355b62f
Summary:
Implements the following intrinsics:
* @llvm.aarch64.sve.brka
* @llvm.aarch64.sve.brka.z
* @llvm.aarch64.sve.brkb
* @llvm.aarch64.sve.brkb.z
* @llvm.aarch64.sve.brkn.z
* @llvm.aarch64.sve.brkpa.z
* @llvm.aarch64.sve.brkpb.z
Reviewers: sdesmalen, efriedma, dancgr, mgudim, cameron.mcinally, rengolin
Reviewed By: sdesmalen
Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72393
228 lines
8.5 KiB
LLVM
228 lines
8.5 KiB
LLVM
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
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;
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; BRKA
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;
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define <vscale x 16 x i1> @brka_m_b8(<vscale x 16 x i1> %inactive, <vscale x 16 x i1> %pg, <vscale x 16 x i1> %a) {
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; CHECK-LABEL: brka_m_b8:
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; CHECK: brka p0.b, p1/m, p2.b
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; CHECK-NEXT: ret
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%out = call <vscale x 16 x i1> @llvm.aarch64.sve.brka.nxv16i1(<vscale x 16 x i1> %inactive,
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<vscale x 16 x i1> %pg,
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<vscale x 16 x i1> %a)
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ret <vscale x 16 x i1> %out
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}
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define <vscale x 16 x i1> @brka_z_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a) {
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; CHECK-LABEL: brka_z_b8:
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; CHECK: brka p0.b, p0/z, p1.b
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; CHECK-NEXT: ret
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%out = call <vscale x 16 x i1> @llvm.aarch64.sve.brka.z.nxv16i1(<vscale x 16 x i1> %pg,
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<vscale x 16 x i1> %a)
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ret <vscale x 16 x i1> %out
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}
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;
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; BRKB
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;
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define <vscale x 16 x i1> @brkb_m_b8(<vscale x 16 x i1> %inactive, <vscale x 16 x i1> %pg, <vscale x 16 x i1> %a) {
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; CHECK-LABEL: brkb_m_b8:
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; CHECK: brkb p0.b, p1/m, p2.b
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; CHECK-NEXT: ret
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%out = call <vscale x 16 x i1> @llvm.aarch64.sve.brkb.nxv16i1(<vscale x 16 x i1> %inactive,
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<vscale x 16 x i1> %pg,
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<vscale x 16 x i1> %a)
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ret <vscale x 16 x i1> %out
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}
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define <vscale x 16 x i1> @brkb_z_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a) {
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; CHECK-LABEL: brkb_z_b8:
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; CHECK: brkb p0.b, p0/z, p1.b
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; CHECK-NEXT: ret
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%out = call <vscale x 16 x i1> @llvm.aarch64.sve.brkb.z.nxv16i1(<vscale x 16 x i1> %pg,
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<vscale x 16 x i1> %a)
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ret <vscale x 16 x i1> %out
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}
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;
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; BRKN
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;
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define <vscale x 16 x i1> @brkn_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
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; CHECK-LABEL: brkn_b8:
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; CHECK: brkn p2.b, p0/z, p1.b, p2.b
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; CHECK-NEXT: mov p0.b, p2.b
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; CHECK-NEXT: ret
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%out = call <vscale x 16 x i1> @llvm.aarch64.sve.brkn.z.nxv16i1(<vscale x 16 x i1> %pg,
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<vscale x 16 x i1> %a,
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<vscale x 16 x i1> %b)
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ret <vscale x 16 x i1> %out
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}
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;
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; BRKPA
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;
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define <vscale x 16 x i1> @brkpa_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
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; CHECK-LABEL: brkpa_b8:
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; CHECK: brkpa p0.b, p0/z, p1.b, p2.b
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; CHECK-NEXT: ret
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%out = call <vscale x 16 x i1> @llvm.aarch64.sve.brkpa.z.nxv16i1(<vscale x 16 x i1> %pg,
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<vscale x 16 x i1> %a,
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<vscale x 16 x i1> %b)
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ret <vscale x 16 x i1> %out
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}
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;
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; BRKPB
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;
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define <vscale x 16 x i1> @brkpb_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
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; CHECK-LABEL: brkpb_b8:
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; CHECK: brkpb p0.b, p0/z, p1.b, p2.b
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; CHECK-NEXT: ret
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%out = call <vscale x 16 x i1> @llvm.aarch64.sve.brkpb.z.nxv16i1(<vscale x 16 x i1> %pg,
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<vscale x 16 x i1> %a,
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<vscale x 16 x i1> %b)
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ret <vscale x 16 x i1> %out
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}
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;
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; PFIRST
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;
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define <vscale x 16 x i1> @pfirst_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a) {
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; CHECK-LABEL: pfirst_b8:
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; CHECK: pfirst p1.b, p0, p1.b
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; CHECK-NEXT: mov p0.b, p1.b
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; CHECK-NEXT: ret
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%out = call <vscale x 16 x i1> @llvm.aarch64.sve.pfirst.nxv16i1(<vscale x 16 x i1> %pg,
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<vscale x 16 x i1> %a)
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ret <vscale x 16 x i1> %out
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}
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;
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; PNEXT
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;
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define <vscale x 16 x i1> @pnext_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a) {
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; CHECK-LABEL: pnext_b8:
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; CHECK: pnext p1.b, p0, p1.b
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; CHECK-NEXT: mov p0.b, p1.b
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; CHECK-NEXT: ret
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%out = call <vscale x 16 x i1> @llvm.aarch64.sve.pnext.nxv16i1(<vscale x 16 x i1> %pg,
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<vscale x 16 x i1> %a)
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ret <vscale x 16 x i1> %out
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}
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define <vscale x 8 x i1> @pnext_b16(<vscale x 8 x i1> %pg, <vscale x 8 x i1> %a) {
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; CHECK-LABEL: pnext_b16:
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; CHECK: pnext p1.h, p0, p1.h
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; CHECK-NEXT: mov p0.b, p1.b
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; CHECK-NEXT: ret
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%out = call <vscale x 8 x i1> @llvm.aarch64.sve.pnext.nxv8i1(<vscale x 8 x i1> %pg,
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<vscale x 8 x i1> %a)
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ret <vscale x 8 x i1> %out
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}
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define <vscale x 4 x i1> @pnext_b32(<vscale x 4 x i1> %pg, <vscale x 4 x i1> %a) {
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; CHECK-LABEL: pnext_b32:
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; CHECK: pnext p1.s, p0, p1.s
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; CHECK-NEXT: mov p0.b, p1.b
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x i1> @llvm.aarch64.sve.pnext.nxv4i1(<vscale x 4 x i1> %pg,
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<vscale x 4 x i1> %a)
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ret <vscale x 4 x i1> %out
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}
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define <vscale x 2 x i1> @pnext_b64(<vscale x 2 x i1> %pg, <vscale x 2 x i1> %a) {
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; CHECK-LABEL: pnext_b64:
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; CHECK: pnext p1.d, p0, p1.d
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; CHECK-NEXT: mov p0.b, p1.b
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; CHECK-NEXT: ret
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%out = call <vscale x 2 x i1> @llvm.aarch64.sve.pnext.nxv2i1(<vscale x 2 x i1> %pg,
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<vscale x 2 x i1> %a)
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ret <vscale x 2 x i1> %out
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}
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;
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; PUNPKHI
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;
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define <vscale x 8 x i1> @punpkhi_b16(<vscale x 16 x i1> %a) {
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; CHECK-LABEL: punpkhi_b16
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; CHECK: punpkhi p0.h, p0.b
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; CHECK-NEXT: ret
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%res = call <vscale x 8 x i1> @llvm.aarch64.sve.punpkhi.nxv8i1(<vscale x 16 x i1> %a)
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ret <vscale x 8 x i1> %res
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}
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define <vscale x 4 x i1> @punpkhi_b8(<vscale x 8 x i1> %a) {
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; CHECK-LABEL: punpkhi_b8
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; CHECK: punpkhi p0.h, p0.b
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; CHECK-NEXT: ret
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%res = call <vscale x 4 x i1> @llvm.aarch64.sve.punpkhi.nxv4i1(<vscale x 8 x i1> %a)
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ret <vscale x 4 x i1> %res
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}
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define <vscale x 2 x i1> @punpkhi_b4(<vscale x 4 x i1> %a) {
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; CHECK-LABEL: punpkhi_b4
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; CHECK: punpkhi p0.h, p0.b
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; CHECK-NEXT: ret
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%res = call <vscale x 2 x i1> @llvm.aarch64.sve.punpkhi.nxv2i1(<vscale x 4 x i1> %a)
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ret <vscale x 2 x i1> %res
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}
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;
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; PUNPKLO
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;
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define <vscale x 8 x i1> @punpklo_b16(<vscale x 16 x i1> %a) {
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; CHECK-LABEL: punpklo_b16
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; CHECK: punpklo p0.h, p0.b
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; CHECK-NEXT: ret
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%res = call <vscale x 8 x i1> @llvm.aarch64.sve.punpklo.nxv8i1(<vscale x 16 x i1> %a)
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ret <vscale x 8 x i1> %res
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}
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define <vscale x 4 x i1> @punpklo_b8(<vscale x 8 x i1> %a) {
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; CHECK-LABEL: punpklo_b8
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; CHECK: punpklo p0.h, p0.b
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; CHECK-NEXT: ret
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%res = call <vscale x 4 x i1> @llvm.aarch64.sve.punpklo.nxv4i1(<vscale x 8 x i1> %a)
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ret <vscale x 4 x i1> %res
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}
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define <vscale x 2 x i1> @punpklo_b4(<vscale x 4 x i1> %a) {
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; CHECK-LABEL: punpklo_b4
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; CHECK: punpklo p0.h, p0.b
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; CHECK-NEXT: ret
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%res = call <vscale x 2 x i1> @llvm.aarch64.sve.punpklo.nxv2i1(<vscale x 4 x i1> %a)
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ret <vscale x 2 x i1> %res
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}
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declare <vscale x 16 x i1> @llvm.aarch64.sve.brka.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>)
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declare <vscale x 16 x i1> @llvm.aarch64.sve.brka.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>)
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declare <vscale x 16 x i1> @llvm.aarch64.sve.brkb.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>)
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declare <vscale x 16 x i1> @llvm.aarch64.sve.brkb.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>)
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declare <vscale x 16 x i1> @llvm.aarch64.sve.brkn.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>)
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declare <vscale x 16 x i1> @llvm.aarch64.sve.brkpa.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>)
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declare <vscale x 16 x i1> @llvm.aarch64.sve.brkpb.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>)
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declare <vscale x 16 x i1> @llvm.aarch64.sve.pfirst.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>)
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declare <vscale x 16 x i1> @llvm.aarch64.sve.pnext.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>)
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declare <vscale x 8 x i1> @llvm.aarch64.sve.pnext.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>)
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declare <vscale x 4 x i1> @llvm.aarch64.sve.pnext.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>)
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declare <vscale x 2 x i1> @llvm.aarch64.sve.pnext.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>)
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declare <vscale x 8 x i1> @llvm.aarch64.sve.punpkhi.nxv8i1(<vscale x 16 x i1>)
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declare <vscale x 4 x i1> @llvm.aarch64.sve.punpkhi.nxv4i1(<vscale x 8 x i1>)
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declare <vscale x 2 x i1> @llvm.aarch64.sve.punpkhi.nxv2i1(<vscale x 4 x i1>)
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declare <vscale x 8 x i1> @llvm.aarch64.sve.punpklo.nxv8i1(<vscale x 16 x i1>)
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declare <vscale x 4 x i1> @llvm.aarch64.sve.punpklo.nxv4i1(<vscale x 8 x i1>)
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declare <vscale x 2 x i1> @llvm.aarch64.sve.punpklo.nxv2i1(<vscale x 4 x i1>)
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