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6aa69a8001
MVE includes instructions that extract an 8- or 16-bit lane from a vector and sign-extend it into the output 32-bit GPR. `ARMInstrMVE.td` already included isel patterns to select those instructions in response to the `ARMISD::VGETLANEs` selection-DAG node type. But `ARMISD::VGETLANEs` was never actually generated, because the code that creates it was conditioned on NEON only. It's an easy fix to enable the same code for integer MVE, and now IR that sign-extends the result of an extractelement (whether explicitly or as part of the function call ABI) will use `vmov.s8` instead of `vmov.u8` followed by `sxtb`. Reviewers: SjoerdMeijer, dmgreen, ostannard Subscribers: kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70132
87 lines
2.3 KiB
LLVM
87 lines
2.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s
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define arm_aapcs_vfpcc i32 @u8_explicit_extend(<16 x i8> %a) {
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; CHECK-LABEL: u8_explicit_extend:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.u8 r0, q0[10]
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; CHECK-NEXT: bx lr
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entry:
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%0 = extractelement <16 x i8> %a, i32 10
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%1 = zext i8 %0 to i32
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ret i32 %1
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}
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define arm_aapcs_vfpcc i32 @s8_explicit_extend(<16 x i8> %a) {
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; CHECK-LABEL: s8_explicit_extend:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.s8 r0, q0[10]
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; CHECK-NEXT: bx lr
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entry:
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%0 = extractelement <16 x i8> %a, i32 10
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%1 = sext i8 %0 to i32
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ret i32 %1
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}
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define arm_aapcs_vfpcc i8 @u8_extend_via_pcs(<16 x i8> %a) {
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; CHECK-LABEL: u8_extend_via_pcs:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.u8 r0, q0[10]
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; CHECK-NEXT: bx lr
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entry:
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%0 = extractelement <16 x i8> %a, i32 10
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ret i8 %0
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}
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define arm_aapcs_vfpcc signext i8 @s8_extend_via_pcs(<16 x i8> %a) {
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; CHECK-LABEL: s8_extend_via_pcs:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.s8 r0, q0[10]
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; CHECK-NEXT: bx lr
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entry:
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%0 = extractelement <16 x i8> %a, i32 10
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ret i8 %0
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}
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define arm_aapcs_vfpcc i32 @u16_explicit_extend(<8 x i16> %a) {
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; CHECK-LABEL: u16_explicit_extend:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.u16 r0, q0[5]
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; CHECK-NEXT: bx lr
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entry:
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%0 = extractelement <8 x i16> %a, i32 5
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%1 = zext i16 %0 to i32
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ret i32 %1
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}
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define arm_aapcs_vfpcc i32 @s16_explicit_extend(<8 x i16> %a) {
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; CHECK-LABEL: s16_explicit_extend:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.s16 r0, q0[5]
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; CHECK-NEXT: bx lr
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entry:
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%0 = extractelement <8 x i16> %a, i32 5
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%1 = sext i16 %0 to i32
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ret i32 %1
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}
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define arm_aapcs_vfpcc i16 @u16_extend_via_pcs(<8 x i16> %a) {
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; CHECK-LABEL: u16_extend_via_pcs:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.u16 r0, q0[5]
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; CHECK-NEXT: bx lr
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entry:
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%0 = extractelement <8 x i16> %a, i32 5
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ret i16 %0
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}
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define arm_aapcs_vfpcc signext i16 @s16_extend_via_pcs(<8 x i16> %a) {
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; CHECK-LABEL: s16_extend_via_pcs:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.s16 r0, q0[5]
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; CHECK-NEXT: bx lr
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entry:
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%0 = extractelement <8 x i16> %a, i32 5
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ret i16 %0
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}
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