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2d0e359316
Summary:
Better use of multiclass is used, and this helped find some existing
bugs in the predicated VMULL* intrinsics, which are now fixed.
The refactored VMULL[TB]Q_(INT|POLY)_M() intrinsics were discovered
to have an argument ("inactive") with incorrect type, and this required
a fix that is included in this whole patch. The argument "inactive"
should have been the same width (per vector element) as the return
type of the intrinsic, but was not in the case where the return type
was double the element width of the input types.
To assist in testing the multiclassing , and to thwart further gremlins,
the unit tests are improved in scope.
The *.ll tests are all generated by a small bit of throw-away scripting
from the corresponding *.c tests, and as such the diffs are large and
nasty. Look at the file rather than the diff.
Reviewers: dmgreen, miyuki, ostannard, simon_tatham
Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D71421
182 lines
6.8 KiB
LLVM
182 lines
6.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s
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define arm_aapcs_vfpcc <16 x i8> @test_vbicq_u8(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 {
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; CHECK-LABEL: test_vbicq_u8:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vbic q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%0 = xor <16 x i8> %b, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
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%1 = and <16 x i8> %0, %a
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ret <16 x i8> %1
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}
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define arm_aapcs_vfpcc <8 x i16> @test_vbicq_s16(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr #0 {
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; CHECK-LABEL: test_vbicq_s16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vbic q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%0 = xor <8 x i16> %b, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
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%1 = and <8 x i16> %0, %a
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ret <8 x i16> %1
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}
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define arm_aapcs_vfpcc <4 x i32> @test_vbicq_u32(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr #0 {
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; CHECK-LABEL: test_vbicq_u32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vbic q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%0 = xor <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1>
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%1 = and <4 x i32> %0, %a
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ret <4 x i32> %1
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}
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define arm_aapcs_vfpcc <4 x float> @test_vbicq_f32(<4 x float> %a, <4 x float> %b) local_unnamed_addr #0 {
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; CHECK-LABEL: test_vbicq_f32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vbic q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%0 = bitcast <4 x float> %a to <4 x i32>
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%1 = bitcast <4 x float> %b to <4 x i32>
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%2 = xor <4 x i32> %1, <i32 -1, i32 -1, i32 -1, i32 -1>
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%3 = and <4 x i32> %2, %0
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%4 = bitcast <4 x i32> %3 to <4 x float>
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ret <4 x float> %4
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}
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define arm_aapcs_vfpcc <16 x i8> @test_vbicq_m_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #1 {
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; CHECK-LABEL: test_vbicq_m_s8:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmsr p0, r0
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vbict q0, q1, q2
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; CHECK-NEXT: bx lr
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entry:
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%0 = zext i16 %p to i32
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%1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
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%2 = tail call <16 x i8> @llvm.arm.mve.bic.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, <16 x i1> %1, <16 x i8> %inactive)
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ret <16 x i8> %2
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}
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declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2
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declare <16 x i8> @llvm.arm.mve.bic.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #2
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define arm_aapcs_vfpcc <8 x i16> @test_vbicq_m_u16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #1 {
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; CHECK-LABEL: test_vbicq_m_u16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmsr p0, r0
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vbict q0, q1, q2
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; CHECK-NEXT: bx lr
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entry:
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%0 = zext i16 %p to i32
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%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
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%2 = tail call <8 x i16> @llvm.arm.mve.bic.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i1> %1, <8 x i16> %inactive)
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ret <8 x i16> %2
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}
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declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
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declare <8 x i16> @llvm.arm.mve.bic.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #2
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define arm_aapcs_vfpcc <4 x i32> @test_vbicq_m_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #1 {
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; CHECK-LABEL: test_vbicq_m_s32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmsr p0, r0
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vbict q0, q1, q2
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; CHECK-NEXT: bx lr
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entry:
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%0 = zext i16 %p to i32
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%1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
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%2 = tail call <4 x i32> @llvm.arm.mve.bic.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i1> %1, <4 x i32> %inactive)
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ret <4 x i32> %2
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}
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declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
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declare <4 x i32> @llvm.arm.mve.bic.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #2
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define arm_aapcs_vfpcc <8 x half> @test_vbicq_m_f16(<8 x half> %inactive, <8 x half> %a, <8 x half> %b, i16 zeroext %p) local_unnamed_addr #1 {
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; CHECK-LABEL: test_vbicq_m_f16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmsr p0, r0
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vbict q0, q1, q2
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; CHECK-NEXT: bx lr
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entry:
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%0 = bitcast <8 x half> %a to <8 x i16>
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%1 = bitcast <8 x half> %b to <8 x i16>
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%2 = zext i16 %p to i32
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%3 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
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%4 = bitcast <8 x half> %inactive to <8 x i16>
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%5 = tail call <8 x i16> @llvm.arm.mve.bic.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %3, <8 x i16> %4)
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%6 = bitcast <8 x i16> %5 to <8 x half>
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ret <8 x half> %6
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}
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define arm_aapcs_vfpcc <16 x i8> @test_vbicq_x_u8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #1 {
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; CHECK-LABEL: test_vbicq_x_u8:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmsr p0, r0
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vbict q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%0 = zext i16 %p to i32
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%1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
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%2 = tail call <16 x i8> @llvm.arm.mve.bic.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, <16 x i1> %1, <16 x i8> undef)
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ret <16 x i8> %2
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}
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define arm_aapcs_vfpcc <8 x i16> @test_vbicq_x_s16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #1 {
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; CHECK-LABEL: test_vbicq_x_s16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmsr p0, r0
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vbict q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%0 = zext i16 %p to i32
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%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
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%2 = tail call <8 x i16> @llvm.arm.mve.bic.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i1> %1, <8 x i16> undef)
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ret <8 x i16> %2
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}
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define arm_aapcs_vfpcc <4 x i32> @test_vbicq_x_u32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #1 {
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; CHECK-LABEL: test_vbicq_x_u32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmsr p0, r0
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vbict q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%0 = zext i16 %p to i32
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%1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
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%2 = tail call <4 x i32> @llvm.arm.mve.bic.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i1> %1, <4 x i32> undef)
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ret <4 x i32> %2
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}
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define arm_aapcs_vfpcc <4 x float> @test_vbicq_m_f32(<4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #1 {
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; CHECK-LABEL: test_vbicq_m_f32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmsr p0, r0
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vbict q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%0 = bitcast <4 x float> %a to <4 x i32>
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%1 = bitcast <4 x float> %b to <4 x i32>
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%2 = zext i16 %p to i32
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%3 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
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%4 = tail call <4 x i32> @llvm.arm.mve.bic.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %3, <4 x i32> undef)
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%5 = bitcast <4 x i32> %4 to <4 x float>
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ret <4 x float> %5
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}
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