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1cded6547c
Summary: This patch adds a new MVE intrinsics family, `vbrsrq`: vector bit reverse and shift right. The intrinsics are compiled into the VBRSR instruction. Two new LLVM IR intrinsics were also added: arm.mve.vbrsr and arm.mve.vbrsr.predicated. Reviewers: simon_tatham, dmgreen, ostannard, MarkMurrayARM Reviewed By: simon_tatham Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D74721
90 lines
3.5 KiB
LLVM
90 lines
3.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s
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declare <8 x half> @llvm.arm.mve.vbrsr.v8f16(<8 x half>, i32)
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declare <4 x i32> @llvm.arm.mve.vbrsr.v4i32(<4 x i32>, i32)
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declare <16 x i8> @llvm.arm.mve.vbrsr.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>)
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declare <8 x i16> @llvm.arm.mve.vbrsr.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>)
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declare <4 x float> @llvm.arm.mve.vbrsr.predicated.v4f32.v4i1(<4 x float>, <4 x float>, i32, <4 x i1>)
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declare <8 x half> @llvm.arm.mve.vbrsr.predicated.v8f16.v8i1(<8 x half>, <8 x half>, i32, <8 x i1>)
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declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32)
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declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32)
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declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)
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define arm_aapcs_vfpcc <4 x i32> @test_vbrsrq_n_u32(<4 x i32> %a, i32 %b) {
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; CHECK-LABEL: test_vbrsrq_n_u32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vbrsr.32 q0, q0, r0
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; CHECK-NEXT: bx lr
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entry:
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%0 = call <4 x i32> @llvm.arm.mve.vbrsr.v4i32(<4 x i32> %a, i32 %b)
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ret <4 x i32> %0
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}
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define arm_aapcs_vfpcc <8 x half> @test_vbrsrq_n_f16(<8 x half> %a, i32 %b) {
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; CHECK-LABEL: test_vbrsrq_n_f16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vbrsr.16 q0, q0, r0
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; CHECK-NEXT: bx lr
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entry:
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%0 = call <8 x half> @llvm.arm.mve.vbrsr.v8f16(<8 x half> %a, i32 %b)
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ret <8 x half> %0
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}
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define arm_aapcs_vfpcc <16 x i8> @test_vbrsrq_m_n_s8(<16 x i8> %inactive, <16 x i8> %a, i32 %b, i16 zeroext %p) {
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; CHECK-LABEL: test_vbrsrq_m_n_s8:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmsr p0, r1
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vbrsrt.8 q0, q1, r0
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; CHECK-NEXT: bx lr
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entry:
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%0 = zext i16 %p to i32
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%1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
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%2 = call <16 x i8> @llvm.arm.mve.vbrsr.predicated.v16i8.v16i1(<16 x i8> %inactive, <16 x i8> %a, i32 %b, <16 x i1> %1)
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ret <16 x i8> %2
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}
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define arm_aapcs_vfpcc <4 x float> @test_vbrsrq_m_n_f32(<4 x float> %inactive, <4 x float> %a, i32 %b, i16 zeroext %p) {
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; CHECK-LABEL: test_vbrsrq_m_n_f32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmsr p0, r1
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vbrsrt.32 q0, q1, r0
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; CHECK-NEXT: bx lr
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entry:
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%0 = zext i16 %p to i32
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%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
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%2 = call <4 x float> @llvm.arm.mve.vbrsr.predicated.v4f32.v4i1(<4 x float> %inactive, <4 x float> %a, i32 %b, <4 x i1> %1)
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ret <4 x float> %2
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}
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define arm_aapcs_vfpcc <8 x i16> @test_vbrsrq_x_n_u16(<8 x i16> %a, i32 %b, i16 zeroext %p) {
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; CHECK-LABEL: test_vbrsrq_x_n_u16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmsr p0, r1
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vbrsrt.16 q0, q0, r0
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; CHECK-NEXT: bx lr
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entry:
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%0 = zext i16 %p to i32
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%1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
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%2 = call <8 x i16> @llvm.arm.mve.vbrsr.predicated.v8i16.v8i1(<8 x i16> undef, <8 x i16> %a, i32 %b, <8 x i1> %1)
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ret <8 x i16> %2
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}
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define arm_aapcs_vfpcc <8 x half> @test_vbrsrq_x_n_f16(<8 x half> %a, i32 %b, i16 zeroext %p) {
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; CHECK-LABEL: test_vbrsrq_x_n_f16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmsr p0, r1
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vbrsrt.16 q0, q0, r0
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; CHECK-NEXT: bx lr
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entry:
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%0 = zext i16 %p to i32
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%1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
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%2 = call <8 x half> @llvm.arm.mve.vbrsr.predicated.v8f16.v8i1(<8 x half> undef, <8 x half> %a, i32 %b, <8 x i1> %1)
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ret <8 x half> %2
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}
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