mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-23 11:13:28 +01:00
53c0143e5a
This adds Post inc variants of the VLD2/4 and VST2/4 instructions in MVE. It uses the same mechanism/nodes as Neon, transforming the intrinsic+add pair into a ARMISD::VLD2_UPD, which gets selected to a post-inc instruction. The code to do that is mostly taken from the existing Neon code, but simplified as less variants are needed. It also fills in some getTgtMemIntrinsic for the arm.mve.vld2/4 instrinsics, which allow the nodes to have MMO's, calculated as the full length to the memory being loaded/stored. Differential Revision: https://reviews.llvm.org/D71194
251 lines
12 KiB
LLVM
251 lines
12 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp,+fp64 -mve-max-interleave-factor=4 -verify-machineinstrs %s -o - | FileCheck %s
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; i32
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define <16 x i32> *@vst4_v4i32(<4 x i32> *%src, <16 x i32> *%dst) {
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; CHECK-LABEL: vst4_v4i32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vldrw.u32 q3, [r0, #48]
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; CHECK-NEXT: vldrw.u32 q2, [r0, #32]
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; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
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; CHECK-NEXT: vldrw.u32 q0, [r0]
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; CHECK-NEXT: vst40.32 {q0, q1, q2, q3}, [r1]
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; CHECK-NEXT: vst41.32 {q0, q1, q2, q3}, [r1]
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; CHECK-NEXT: vst42.32 {q0, q1, q2, q3}, [r1]
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; CHECK-NEXT: vst43.32 {q0, q1, q2, q3}, [r1]!
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; CHECK-NEXT: mov r0, r1
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; CHECK-NEXT: bx lr
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entry:
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%s1 = getelementptr <4 x i32>, <4 x i32>* %src, i32 0
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%l1 = load <4 x i32>, <4 x i32>* %s1, align 4
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%s2 = getelementptr <4 x i32>, <4 x i32>* %src, i32 1
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%l2 = load <4 x i32>, <4 x i32>* %s2, align 4
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%s3 = getelementptr <4 x i32>, <4 x i32>* %src, i32 2
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%l3 = load <4 x i32>, <4 x i32>* %s3, align 4
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%s4 = getelementptr <4 x i32>, <4 x i32>* %src, i32 3
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%l4 = load <4 x i32>, <4 x i32>* %s4, align 4
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%t1 = shufflevector <4 x i32> %l1, <4 x i32> %l2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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%t2 = shufflevector <4 x i32> %l3, <4 x i32> %l4, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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%s = shufflevector <8 x i32> %t1, <8 x i32> %t2, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 1, i32 5, i32 9, i32 13, i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15>
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store <16 x i32> %s, <16 x i32> *%dst
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%ret = getelementptr inbounds <16 x i32>, <16 x i32>* %dst, i32 1
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ret <16 x i32> *%ret
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}
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; i16
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define <32 x i16> *@vst4_v8i16(<8 x i16> *%src, <32 x i16> *%dst) {
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; CHECK-LABEL: vst4_v8i16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vldrw.u32 q3, [r0, #48]
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; CHECK-NEXT: vldrw.u32 q2, [r0, #32]
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; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
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; CHECK-NEXT: vldrw.u32 q0, [r0]
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; CHECK-NEXT: vst40.16 {q0, q1, q2, q3}, [r1]
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; CHECK-NEXT: vst41.16 {q0, q1, q2, q3}, [r1]
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; CHECK-NEXT: vst42.16 {q0, q1, q2, q3}, [r1]
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; CHECK-NEXT: vst43.16 {q0, q1, q2, q3}, [r1]!
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; CHECK-NEXT: mov r0, r1
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; CHECK-NEXT: bx lr
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entry:
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%s1 = getelementptr <8 x i16>, <8 x i16>* %src, i32 0
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%l1 = load <8 x i16>, <8 x i16>* %s1, align 4
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%s2 = getelementptr <8 x i16>, <8 x i16>* %src, i32 1
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%l2 = load <8 x i16>, <8 x i16>* %s2, align 4
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%s3 = getelementptr <8 x i16>, <8 x i16>* %src, i32 2
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%l3 = load <8 x i16>, <8 x i16>* %s3, align 4
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%s4 = getelementptr <8 x i16>, <8 x i16>* %src, i32 3
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%l4 = load <8 x i16>, <8 x i16>* %s4, align 4
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%t1 = shufflevector <8 x i16> %l1, <8 x i16> %l2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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%t2 = shufflevector <8 x i16> %l3, <8 x i16> %l4, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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%s = shufflevector <16 x i16> %t1, <16 x i16> %t2, <32 x i32> <i32 0, i32 8, i32 16, i32 24, i32 1, i32 9, i32 17, i32 25, i32 2, i32 10, i32 18, i32 26, i32 3, i32 11, i32 19, i32 27, i32 4, i32 12, i32 20, i32 28, i32 5, i32 13, i32 21, i32 29, i32 6, i32 14, i32 22, i32 30, i32 7, i32 15, i32 23, i32 31>
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store <32 x i16> %s, <32 x i16> *%dst
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%ret = getelementptr inbounds <32 x i16>, <32 x i16>* %dst, i32 1
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ret <32 x i16> *%ret
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}
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; i8
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define <64 x i8> *@vst4_v16i8(<16 x i8> *%src, <64 x i8> *%dst) {
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; CHECK-LABEL: vst4_v16i8:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vldrw.u32 q3, [r0, #48]
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; CHECK-NEXT: vldrw.u32 q2, [r0, #32]
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; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
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; CHECK-NEXT: vldrw.u32 q0, [r0]
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; CHECK-NEXT: vst40.8 {q0, q1, q2, q3}, [r1]
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; CHECK-NEXT: vst41.8 {q0, q1, q2, q3}, [r1]
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; CHECK-NEXT: vst42.8 {q0, q1, q2, q3}, [r1]
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; CHECK-NEXT: vst43.8 {q0, q1, q2, q3}, [r1]!
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; CHECK-NEXT: mov r0, r1
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; CHECK-NEXT: bx lr
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entry:
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%s1 = getelementptr <16 x i8>, <16 x i8>* %src, i32 0
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%l1 = load <16 x i8>, <16 x i8>* %s1, align 4
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%s2 = getelementptr <16 x i8>, <16 x i8>* %src, i32 1
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%l2 = load <16 x i8>, <16 x i8>* %s2, align 4
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%s3 = getelementptr <16 x i8>, <16 x i8>* %src, i32 2
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%l3 = load <16 x i8>, <16 x i8>* %s3, align 4
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%s4 = getelementptr <16 x i8>, <16 x i8>* %src, i32 3
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%l4 = load <16 x i8>, <16 x i8>* %s4, align 4
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%t1 = shufflevector <16 x i8> %l1, <16 x i8> %l2, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
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%t2 = shufflevector <16 x i8> %l3, <16 x i8> %l4, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
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%s = shufflevector <32 x i8> %t1, <32 x i8> %t2, <64 x i32> <i32 0, i32 16, i32 32, i32 48, i32 1, i32 17, i32 33, i32 49, i32 2, i32 18, i32 34, i32 50, i32 3, i32 19, i32 35, i32 51, i32 4, i32 20, i32 36, i32 52, i32 5, i32 21, i32 37, i32 53, i32 6, i32 22, i32 38, i32 54, i32 7, i32 23, i32 39, i32 55, i32 8, i32 24, i32 40, i32 56, i32 9, i32 25, i32 41, i32 57, i32 10, i32 26, i32 42, i32 58, i32 11, i32 27, i32 43, i32 59, i32 12, i32 28, i32 44, i32 60, i32 13, i32 29, i32 45, i32 61, i32 14, i32 30, i32 46, i32 62, i32 15, i32 31, i32 47, i32 63>
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store <64 x i8> %s, <64 x i8> *%dst
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%ret = getelementptr inbounds <64 x i8>, <64 x i8>* %dst, i32 1
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ret <64 x i8> *%ret
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}
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; i64
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define <8 x i64> *@vst4_v2i64(<2 x i64> *%src, <8 x i64> *%dst) {
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; CHECK-LABEL: vst4_v2i64:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .vsave {d8, d9}
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; CHECK-NEXT: vpush {d8, d9}
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; CHECK-NEXT: vldrw.u32 q4, [r0]
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; CHECK-NEXT: vldrw.u32 q0, [r0, #16]
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; CHECK-NEXT: vldrw.u32 q3, [r0, #32]
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; CHECK-NEXT: vldrw.u32 q1, [r0, #48]
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; CHECK-NEXT: vmov.f64 d4, d8
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; CHECK-NEXT: add.w r0, r1, #64
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; CHECK-NEXT: vmov.f32 s9, s17
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; CHECK-NEXT: vmov.f32 s10, s0
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; CHECK-NEXT: vmov.f32 s11, s1
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; CHECK-NEXT: vmov.f32 s0, s18
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; CHECK-NEXT: vstrw.32 q2, [r1]
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; CHECK-NEXT: vmov.f32 s1, s19
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; CHECK-NEXT: vmov.f64 d8, d6
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; CHECK-NEXT: vstrw.32 q0, [r1, #32]
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; CHECK-NEXT: vmov.f32 s17, s13
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; CHECK-NEXT: vmov.f32 s18, s4
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; CHECK-NEXT: vmov.f32 s19, s5
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; CHECK-NEXT: vmov.f32 s4, s14
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; CHECK-NEXT: vstrw.32 q4, [r1, #16]
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; CHECK-NEXT: vmov.f32 s5, s15
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; CHECK-NEXT: vstrw.32 q1, [r1, #48]
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; CHECK-NEXT: vpop {d8, d9}
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; CHECK-NEXT: bx lr
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entry:
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%s1 = getelementptr <2 x i64>, <2 x i64>* %src, i32 0
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%l1 = load <2 x i64>, <2 x i64>* %s1, align 4
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%s2 = getelementptr <2 x i64>, <2 x i64>* %src, i32 1
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%l2 = load <2 x i64>, <2 x i64>* %s2, align 4
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%s3 = getelementptr <2 x i64>, <2 x i64>* %src, i32 2
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%l3 = load <2 x i64>, <2 x i64>* %s3, align 4
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%s4 = getelementptr <2 x i64>, <2 x i64>* %src, i32 3
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%l4 = load <2 x i64>, <2 x i64>* %s4, align 4
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%t1 = shufflevector <2 x i64> %l1, <2 x i64> %l2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%t2 = shufflevector <2 x i64> %l3, <2 x i64> %l4, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%s = shufflevector <4 x i64> %t1, <4 x i64> %t2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7>
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store <8 x i64> %s, <8 x i64> *%dst
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%ret = getelementptr inbounds <8 x i64>, <8 x i64>* %dst, i32 1
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ret <8 x i64> *%ret
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}
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; f32
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define <16 x float> *@vst4_v4f32(<4 x float> *%src, <16 x float> *%dst) {
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; CHECK-LABEL: vst4_v4f32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vldrw.u32 q3, [r0, #48]
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; CHECK-NEXT: vldrw.u32 q2, [r0, #32]
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; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
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; CHECK-NEXT: vldrw.u32 q0, [r0]
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; CHECK-NEXT: vst40.32 {q0, q1, q2, q3}, [r1]
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; CHECK-NEXT: vst41.32 {q0, q1, q2, q3}, [r1]
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; CHECK-NEXT: vst42.32 {q0, q1, q2, q3}, [r1]
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; CHECK-NEXT: vst43.32 {q0, q1, q2, q3}, [r1]!
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; CHECK-NEXT: mov r0, r1
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; CHECK-NEXT: bx lr
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entry:
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%s1 = getelementptr <4 x float>, <4 x float>* %src, i32 0
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%l1 = load <4 x float>, <4 x float>* %s1, align 4
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%s2 = getelementptr <4 x float>, <4 x float>* %src, i32 1
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%l2 = load <4 x float>, <4 x float>* %s2, align 4
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%s3 = getelementptr <4 x float>, <4 x float>* %src, i32 2
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%l3 = load <4 x float>, <4 x float>* %s3, align 4
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%s4 = getelementptr <4 x float>, <4 x float>* %src, i32 3
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%l4 = load <4 x float>, <4 x float>* %s4, align 4
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%t1 = shufflevector <4 x float> %l1, <4 x float> %l2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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%t2 = shufflevector <4 x float> %l3, <4 x float> %l4, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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%s = shufflevector <8 x float> %t1, <8 x float> %t2, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 1, i32 5, i32 9, i32 13, i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15>
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store <16 x float> %s, <16 x float> *%dst
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%ret = getelementptr inbounds <16 x float>, <16 x float>* %dst, i32 1
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ret <16 x float> *%ret
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}
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; f16
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define <32 x half> *@vst4_v8f16(<8 x half> *%src, <32 x half> *%dst) {
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; CHECK-LABEL: vst4_v8f16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vldrw.u32 q3, [r0, #48]
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; CHECK-NEXT: vldrw.u32 q2, [r0, #32]
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; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
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; CHECK-NEXT: vldrw.u32 q0, [r0]
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; CHECK-NEXT: vst40.16 {q0, q1, q2, q3}, [r1]
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; CHECK-NEXT: vst41.16 {q0, q1, q2, q3}, [r1]
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; CHECK-NEXT: vst42.16 {q0, q1, q2, q3}, [r1]
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; CHECK-NEXT: vst43.16 {q0, q1, q2, q3}, [r1]!
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; CHECK-NEXT: mov r0, r1
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; CHECK-NEXT: bx lr
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entry:
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%s1 = getelementptr <8 x half>, <8 x half>* %src, i32 0
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%l1 = load <8 x half>, <8 x half>* %s1, align 4
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%s2 = getelementptr <8 x half>, <8 x half>* %src, i32 1
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%l2 = load <8 x half>, <8 x half>* %s2, align 4
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%s3 = getelementptr <8 x half>, <8 x half>* %src, i32 2
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%l3 = load <8 x half>, <8 x half>* %s3, align 4
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%s4 = getelementptr <8 x half>, <8 x half>* %src, i32 3
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%l4 = load <8 x half>, <8 x half>* %s4, align 4
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%t1 = shufflevector <8 x half> %l1, <8 x half> %l2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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%t2 = shufflevector <8 x half> %l3, <8 x half> %l4, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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%s = shufflevector <16 x half> %t1, <16 x half> %t2, <32 x i32> <i32 0, i32 8, i32 16, i32 24, i32 1, i32 9, i32 17, i32 25, i32 2, i32 10, i32 18, i32 26, i32 3, i32 11, i32 19, i32 27, i32 4, i32 12, i32 20, i32 28, i32 5, i32 13, i32 21, i32 29, i32 6, i32 14, i32 22, i32 30, i32 7, i32 15, i32 23, i32 31>
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store <32 x half> %s, <32 x half> *%dst
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%ret = getelementptr inbounds <32 x half>, <32 x half>* %dst, i32 1
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ret <32 x half> *%ret
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}
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; f64
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define <8 x double> *@vst4_v2f64(<2 x double> *%src, <8 x double> *%dst) {
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; CHECK-LABEL: vst4_v2f64:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .vsave {d8, d9}
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; CHECK-NEXT: vpush {d8, d9}
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; CHECK-NEXT: vldrw.u32 q3, [r0]
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; CHECK-NEXT: vldrw.u32 q0, [r0, #16]
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; CHECK-NEXT: vldrw.u32 q4, [r0, #32]
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; CHECK-NEXT: vldrw.u32 q1, [r0, #48]
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; CHECK-NEXT: vmov.f64 d4, d6
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; CHECK-NEXT: add.w r0, r1, #64
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; CHECK-NEXT: vmov.f64 d5, d0
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; CHECK-NEXT: vmov.f64 d0, d7
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; CHECK-NEXT: vstrw.32 q2, [r1]
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; CHECK-NEXT: vmov.f64 d6, d8
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; CHECK-NEXT: vstrw.32 q0, [r1, #32]
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; CHECK-NEXT: vmov.f64 d7, d2
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; CHECK-NEXT: vmov.f64 d2, d9
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; CHECK-NEXT: vstrw.32 q3, [r1, #16]
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; CHECK-NEXT: vstrw.32 q1, [r1, #48]
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; CHECK-NEXT: vpop {d8, d9}
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; CHECK-NEXT: bx lr
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entry:
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%s1 = getelementptr <2 x double>, <2 x double>* %src, i32 0
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%l1 = load <2 x double>, <2 x double>* %s1, align 4
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%s2 = getelementptr <2 x double>, <2 x double>* %src, i32 1
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%l2 = load <2 x double>, <2 x double>* %s2, align 4
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%s3 = getelementptr <2 x double>, <2 x double>* %src, i32 2
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%l3 = load <2 x double>, <2 x double>* %s3, align 4
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%s4 = getelementptr <2 x double>, <2 x double>* %src, i32 3
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%l4 = load <2 x double>, <2 x double>* %s4, align 4
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%t1 = shufflevector <2 x double> %l1, <2 x double> %l2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%t2 = shufflevector <2 x double> %l3, <2 x double> %l4, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%s = shufflevector <4 x double> %t1, <4 x double> %t2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7>
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store <8 x double> %s, <8 x double> *%dst
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%ret = getelementptr inbounds <8 x double>, <8 x double>* %dst, i32 1
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ret <8 x double> *%ret
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}
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