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AsmParser
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[RISCV] RISCVAsmParser: early exit if RISCVOperand isn't immediate as expected
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2017-10-19 16:22:51 +00:00 |
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Disassembler
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[RISCV] Prepare for the use of variable-sized register classes
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2017-10-19 14:29:03 +00:00 |
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InstPrinter
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[RISCV] Add support for all RV32I instructions
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2017-09-17 14:27:35 +00:00 |
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MCTargetDesc
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[RISCV] Prepare for the use of variable-sized register classes
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2017-10-19 14:29:03 +00:00 |
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TargetInfo
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[RISCV] Add bare-bones RISC-V MCTargetDesc
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2016-11-01 23:47:30 +00:00 |
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CMakeLists.txt
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[RISCV] Initial codegen support for ALU operations
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2017-10-19 21:37:38 +00:00 |
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LLVMBuild.txt
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[RISCV] Initial codegen support for ALU operations
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2017-10-19 21:37:38 +00:00 |
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RISCV.h
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[RISCV] Codegen support for memory operations on global addresses
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2017-11-08 13:24:21 +00:00 |
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RISCV.td
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[NFCI] Ensure TargetOpcode::* are compatible with guessInstructionProperties=0
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2017-11-08 09:26:06 +00:00 |
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RISCVAsmPrinter.cpp
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[RISCV] Codegen support for memory operations on global addresses
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2017-11-08 13:24:21 +00:00 |
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RISCVCallingConv.td
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[RISCV] Initial codegen support for ALU operations
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2017-10-19 21:37:38 +00:00 |
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RISCVFrameLowering.cpp
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[RISCV] Initial codegen support for ALU operations
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2017-10-19 21:37:38 +00:00 |
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RISCVFrameLowering.h
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Move TargetFrameLowering.h to CodeGen where it's implemented
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2017-11-03 22:32:11 +00:00 |
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RISCVInstrFormats.td
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[RISCV] Prepare for the use of variable-sized register classes
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2017-10-19 14:29:03 +00:00 |
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RISCVInstrInfo.cpp
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[RISCV] Codegen support for memory operations
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2017-11-08 12:20:01 +00:00 |
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RISCVInstrInfo.h
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[RISCV] Codegen support for memory operations
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2017-11-08 12:20:01 +00:00 |
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RISCVInstrInfo.td
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[RISCV] Codegen support for memory operations
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2017-11-08 12:20:01 +00:00 |
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RISCVISelDAGToDAG.cpp
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[RISCV] Initial codegen support for ALU operations
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2017-10-19 21:37:38 +00:00 |
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RISCVISelLowering.cpp
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[RISCV] Codegen support for memory operations on global addresses
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2017-11-08 13:24:21 +00:00 |
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RISCVISelLowering.h
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[RISCV] Codegen support for memory operations on global addresses
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2017-11-08 13:24:21 +00:00 |
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RISCVMCInstLower.cpp
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[RISCV] Codegen support for memory operations on global addresses
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2017-11-08 13:24:21 +00:00 |
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RISCVRegisterInfo.cpp
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Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering
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2017-11-08 01:01:31 +00:00 |
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RISCVRegisterInfo.h
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[RISCV] Initial codegen support for ALU operations
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2017-10-19 21:37:38 +00:00 |
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RISCVRegisterInfo.td
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[RISCV] Initial codegen support for ALU operations
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2017-10-19 21:37:38 +00:00 |
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RISCVSubtarget.cpp
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[RISCV] Initial codegen support for ALU operations
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2017-10-19 21:37:38 +00:00 |
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RISCVSubtarget.h
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[RISCV] Initial codegen support for ALU operations
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2017-10-19 21:37:38 +00:00 |
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RISCVTargetMachine.cpp
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[RISCV] Initial codegen support for ALU operations
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2017-10-19 21:37:38 +00:00 |
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RISCVTargetMachine.h
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[RISCV] Initial codegen support for ALU operations
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2017-10-19 21:37:38 +00:00 |
