RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-02-01 05:01:59 +01:00
Code Issues Projects Releases Wiki Activity
llvm-mirror/test/Transforms/InstCombine/pull-conditional-binop-through-shift.ll
Roman Lebedev 6efaf72ba7 [InstCombine] canShiftBinOpWithConstantRHS(): drop bogus signbit check 
Summary:
In D61918 i was looking at dropping it in DAGCombiner `visitShiftByConstant()`,
but as @craig.topper pointed out, it was copied from here.

That check claims that the transform is illegal otherwise.
That isn't true:
1. For `ISD::ADD`, we only process `ISD::SHL` outer shift => sign bit does not matter
   https://rise4fun.com/Alive/K4A
2. For `ISD::AND`, there is no restriction on constants:
   https://rise4fun.com/Alive/Wy3
3. For `ISD::OR`, there is no restriction on constants:
   https://rise4fun.com/Alive/GOH
3. For `ISD::XOR`, there is no restriction on constants:
   https://rise4fun.com/Alive/ml6

So, why is it there then?
As far as i can tell, it dates all the way back to original check-in rL7793.
I think we should just drop it.

Reviewers: spatel, craig.topper, efriedma, majnemer

Reviewed By: spatel

Subscribers: llvm-commits, craig.topper

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D61938

llvm-svn: 361043
2019-05-17 15:52:49 +00:00

309 lines
11 KiB
LLVM
Raw Blame History

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -instcombine -S | FileCheck %s
; shift left
define i32 @and_signbit_select_shl(i32 %x, i1 %cond) {
; CHECK-LABEL: @and_signbit_select_shl(
; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 8
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -16777216
; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
; CHECK-NEXT: ret i32 [[R]]
;
%t0 = and i32 %x, 4294901760 ; 0xFFFF0000
%t1 = select i1 %cond, i32 %t0, i32 %x
%r = shl i32 %t1, 8
ret i32 %r
}
define i32 @and_nosignbit_select_shl(i32 %x, i1 %cond) {
; CHECK-LABEL: @and_nosignbit_select_shl(
; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 8
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -16777216
; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
; CHECK-NEXT: ret i32 [[R]]
;
%t0 = and i32 %x, 2147418112 ; 0x7FFF0000
%t1 = select i1 %cond, i32 %t0, i32 %x
%r = shl i32 %t1, 8
ret i32 %r
}
define i32 @or_signbit_select_shl(i32 %x, i1 %cond) {
; CHECK-LABEL: @or_signbit_select_shl(
; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 8
; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], -16777216
; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
; CHECK-NEXT: ret i32 [[R]]
;
%t0 = or i32 %x, 4294901760 ; 0xFFFF0000
%t1 = select i1 %cond, i32 %t0, i32 %x
%r = shl i32 %t1, 8
ret i32 %r
}
define i32 @or_nosignbit_select_shl(i32 %x, i1 %cond) {
; CHECK-LABEL: @or_nosignbit_select_shl(
; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 8
; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], -16777216
; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
; CHECK-NEXT: ret i32 [[R]]
;
%t0 = or i32 %x, 2147418112 ; 0x7FFF0000
%t1 = select i1 %cond, i32 %t0, i32 %x
%r = shl i32 %t1, 8
ret i32 %r
}
define i32 @xor_signbit_select_shl(i32 %x, i1 %cond) {
; CHECK-LABEL: @xor_signbit_select_shl(
; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 8
; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], -16777216
; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
; CHECK-NEXT: ret i32 [[R]]
;
%t0 = xor i32 %x, 4294901760 ; 0xFFFF0000
%t1 = select i1 %cond, i32 %t0, i32 %x
%r = shl i32 %t1, 8
ret i32 %r
}
define i32 @xor_nosignbit_select_shl(i32 %x, i1 %cond) {
; CHECK-LABEL: @xor_nosignbit_select_shl(
; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 8
; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], -16777216
; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
; CHECK-NEXT: ret i32 [[R]]
;
%t0 = xor i32 %x, 2147418112 ; 0x7FFF0000
%t1 = select i1 %cond, i32 %t0, i32 %x
%r = shl i32 %t1, 8
ret i32 %r
}
define i32 @add_signbit_select_shl(i32 %x, i1 %cond) {
; CHECK-LABEL: @add_signbit_select_shl(
; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 8
; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], -16777216
; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
; CHECK-NEXT: ret i32 [[R]]
;
%t0 = add i32 %x, 4294901760 ; 0xFFFF0000
%t1 = select i1 %cond, i32 %t0, i32 %x
%r = shl i32 %t1, 8
ret i32 %r
}
define i32 @add_nosignbit_select_shl(i32 %x, i1 %cond) {
; CHECK-LABEL: @add_nosignbit_select_shl(
; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 8
; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], -16777216
; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
; CHECK-NEXT: ret i32 [[R]]
;
%t0 = add i32 %x, 2147418112 ; 0x7FFF0000
%t1 = select i1 %cond, i32 %t0, i32 %x
%r = shl i32 %t1, 8
ret i32 %r
}
; logical shift right
define i32 @and_signbit_select_lshr(i32 %x, i1 %cond) {
; CHECK-LABEL: @and_signbit_select_lshr(
; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 8
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 16776960
; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
; CHECK-NEXT: ret i32 [[R]]
;
%t0 = and i32 %x, 4294901760 ; 0xFFFF0000
%t1 = select i1 %cond, i32 %t0, i32 %x
%r = lshr i32 %t1, 8
ret i32 %r
}
define i32 @and_nosignbit_select_lshr(i32 %x, i1 %cond) {
; CHECK-LABEL: @and_nosignbit_select_lshr(
; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 8
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 8388352
; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
; CHECK-NEXT: ret i32 [[R]]
;
%t0 = and i32 %x, 2147418112 ; 0x7FFF0000
%t1 = select i1 %cond, i32 %t0, i32 %x
%r = lshr i32 %t1, 8
ret i32 %r
}
define i32 @or_signbit_select_lshr(i32 %x, i1 %cond) {
; CHECK-LABEL: @or_signbit_select_lshr(
; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 8
; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], 16776960
; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
; CHECK-NEXT: ret i32 [[R]]
;
%t0 = or i32 %x, 4294901760 ; 0xFFFF0000
%t1 = select i1 %cond, i32 %t0, i32 %x
%r = lshr i32 %t1, 8
ret i32 %r
}
define i32 @or_nosignbit_select_lshr(i32 %x, i1 %cond) {
; CHECK-LABEL: @or_nosignbit_select_lshr(
; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 8
; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], 8388352
; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
; CHECK-NEXT: ret i32 [[R]]
;
%t0 = or i32 %x, 2147418112 ; 0x7FFF0000
%t1 = select i1 %cond, i32 %t0, i32 %x
%r = lshr i32 %t1, 8
ret i32 %r
}
define i32 @xor_signbit_select_lshr(i32 %x, i1 %cond) {
; CHECK-LABEL: @xor_signbit_select_lshr(
; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 8
; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 16776960
; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
; CHECK-NEXT: ret i32 [[R]]
;
%t0 = xor i32 %x, 4294901760 ; 0xFFFF0000
%t1 = select i1 %cond, i32 %t0, i32 %x
%r = lshr i32 %t1, 8
ret i32 %r
}
define i32 @xor_nosignbit_select_lshr(i32 %x, i1 %cond) {
; CHECK-LABEL: @xor_nosignbit_select_lshr(
; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 8
; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 8388352
; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
; CHECK-NEXT: ret i32 [[R]]
;
%t0 = xor i32 %x, 2147418112 ; 0x7FFF0000
%t1 = select i1 %cond, i32 %t0, i32 %x
%r = lshr i32 %t1, 8
ret i32 %r
}
define i32 @add_signbit_select_lshr(i32 %x, i1 %cond) {
; CHECK-LABEL: @add_signbit_select_lshr(
; CHECK-NEXT: [[T0:%.*]] = add i32 [[X:%.*]], -65536
; CHECK-NEXT: [[T1:%.*]] = select i1 [[COND:%.*]], i32 [[T0]], i32 [[X]]
; CHECK-NEXT: [[R:%.*]] = lshr i32 [[T1]], 8
; CHECK-NEXT: ret i32 [[R]]
;
%t0 = add i32 %x, 4294901760 ; 0xFFFF0000
%t1 = select i1 %cond, i32 %t0, i32 %x
%r = lshr i32 %t1, 8
ret i32 %r
}
define i32 @add_nosignbit_select_lshr(i32 %x, i1 %cond) {
; CHECK-LABEL: @add_nosignbit_select_lshr(
; CHECK-NEXT: [[T0:%.*]] = add i32 [[X:%.*]], 2147418112
; CHECK-NEXT: [[T1:%.*]] = select i1 [[COND:%.*]], i32 [[T0]], i32 [[X]]
; CHECK-NEXT: [[R:%.*]] = lshr i32 [[T1]], 8
; CHECK-NEXT: ret i32 [[R]]
;
%t0 = add i32 %x, 2147418112 ; 0x7FFF0000
%t1 = select i1 %cond, i32 %t0, i32 %x
%r = lshr i32 %t1, 8
ret i32 %r
}
; arithmetic shift right
define i32 @and_signbit_select_ashr(i32 %x, i1 %cond) {
; CHECK-LABEL: @and_signbit_select_ashr(
; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 8
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -256
; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
; CHECK-NEXT: ret i32 [[R]]
;
%t0 = and i32 %x, 4294901760 ; 0xFFFF0000
%t1 = select i1 %cond, i32 %t0, i32 %x
%r = ashr i32 %t1, 8
ret i32 %r
}
define i32 @and_nosignbit_select_ashr(i32 %x, i1 %cond) {
; CHECK-LABEL: @and_nosignbit_select_ashr(
; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 8
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 8388352
; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
; CHECK-NEXT: ret i32 [[R]]
;
%t0 = and i32 %x, 2147418112 ; 0x7FFF0000
%t1 = select i1 %cond, i32 %t0, i32 %x
%r = ashr i32 %t1, 8
ret i32 %r
}
define i32 @or_signbit_select_ashr(i32 %x, i1 %cond) {
; CHECK-LABEL: @or_signbit_select_ashr(
; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 8
; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], -256
; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
; CHECK-NEXT: ret i32 [[R]]
;
%t0 = or i32 %x, 4294901760 ; 0xFFFF0000
%t1 = select i1 %cond, i32 %t0, i32 %x
%r = ashr i32 %t1, 8
ret i32 %r
}
define i32 @or_nosignbit_select_ashr(i32 %x, i1 %cond) {
; CHECK-LABEL: @or_nosignbit_select_ashr(
; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 8
; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], 8388352
; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
; CHECK-NEXT: ret i32 [[R]]
;
%t0 = or i32 %x, 2147418112 ; 0x7FFF0000
%t1 = select i1 %cond, i32 %t0, i32 %x
%r = ashr i32 %t1, 8
ret i32 %r
}
define i32 @xor_signbit_select_ashr(i32 %x, i1 %cond) {
; CHECK-LABEL: @xor_signbit_select_ashr(
; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 8
; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], -256
; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
; CHECK-NEXT: ret i32 [[R]]
;
%t0 = xor i32 %x, 4294901760 ; 0xFFFF0000
%t1 = select i1 %cond, i32 %t0, i32 %x
%r = ashr i32 %t1, 8
ret i32 %r
}
define i32 @xor_nosignbit_select_ashr(i32 %x, i1 %cond) {
; CHECK-LABEL: @xor_nosignbit_select_ashr(
; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 8
; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 8388352
; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
; CHECK-NEXT: ret i32 [[R]]
;
%t0 = xor i32 %x, 2147418112 ; 0x7FFF0000
%t1 = select i1 %cond, i32 %t0, i32 %x
%r = ashr i32 %t1, 8
ret i32 %r
}
define i32 @add_signbit_select_ashr(i32 %x, i1 %cond) {
; CHECK-LABEL: @add_signbit_select_ashr(
; CHECK-NEXT: [[T0:%.*]] = add i32 [[X:%.*]], -65536
; CHECK-NEXT: [[T1:%.*]] = select i1 [[COND:%.*]], i32 [[T0]], i32 [[X]]
; CHECK-NEXT: [[R:%.*]] = ashr i32 [[T1]], 8
; CHECK-NEXT: ret i32 [[R]]
;
%t0 = add i32 %x, 4294901760 ; 0xFFFF0000
%t1 = select i1 %cond, i32 %t0, i32 %x
%r = ashr i32 %t1, 8
ret i32 %r
}
define i32 @add_nosignbit_select_ashr(i32 %x, i1 %cond) {
; CHECK-LABEL: @add_nosignbit_select_ashr(
; CHECK-NEXT: [[T0:%.*]] = add i32 [[X:%.*]], 2147418112
; CHECK-NEXT: [[T1:%.*]] = select i1 [[COND:%.*]], i32 [[T0]], i32 [[X]]
; CHECK-NEXT: [[R:%.*]] = ashr i32 [[T1]], 8
; CHECK-NEXT: ret i32 [[R]]
;
%t0 = add i32 %x, 2147418112 ; 0x7FFF0000
%t1 = select i1 %cond, i32 %t0, i32 %x
%r = ashr i32 %t1, 8
ret i32 %r
}
Reference in New Issue View Git Blame Copy Permalink