mirror of
https://github.com/RPCS3/llvm-mirror.git
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2bd190f7f1
Summary: Fold and(ashr(subNSW(Y, X), ScalarSizeInBits(Y)-1), X) into X s> Y ? X : 0 https://rise4fun.com/Alive/lFH Fold shift into select enables more optimization, e.g., vmax generation for ARM target. Reviewers: lebedev.ri, efriedma, spatel, kparzysz, bcahoon Reviewed By: lebedev.ri Subscribers: xbolva00, andreadb, craig.topper, RKSimon, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67799 llvm-svn: 372676
214 lines
6.7 KiB
LLVM
214 lines
6.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -instcombine %s -S -o - | FileCheck %s
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; Clamp negative to zero:
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; E.g., clamp0 implemented in a shifty way, could be optimized as v > 0 ? v : 0, where sub hasNoSignedWrap.
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; int32 clamp0(int32 v) {
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; return ((-(v) >> 31) & (v));
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; }
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;
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; Scalar Types
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define i8 @sub_ashr_and_i8(i8 %x, i8 %y) {
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; CHECK-LABEL: @sub_ashr_and_i8(
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; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i8 [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: [[AND:%.*]] = select i1 [[TMP1]], i8 [[X]], i8 0
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; CHECK-NEXT: ret i8 [[AND]]
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;
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%sub = sub nsw i8 %y, %x
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%shr = ashr i8 %sub, 7
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%and = and i8 %shr, %x
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ret i8 %and
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}
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define i16 @sub_ashr_and_i16(i16 %x, i16 %y) {
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; CHECK-LABEL: @sub_ashr_and_i16(
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; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i16 [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: [[AND:%.*]] = select i1 [[TMP1]], i16 [[X]], i16 0
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; CHECK-NEXT: ret i16 [[AND]]
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;
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%sub = sub nsw i16 %y, %x
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%shr = ashr i16 %sub, 15
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%and = and i16 %shr, %x
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ret i16 %and
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}
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define i32 @sub_ashr_and_i32(i32 %x, i32 %y) {
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; CHECK-LABEL: @sub_ashr_and_i32(
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; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: [[AND:%.*]] = select i1 [[TMP1]], i32 [[X]], i32 0
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; CHECK-NEXT: ret i32 [[AND]]
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;
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%sub = sub nsw i32 %y, %x
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%shr = ashr i32 %sub, 31
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%and = and i32 %shr, %x
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ret i32 %and
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}
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define i64 @sub_ashr_and_i64(i64 %x, i64 %y) {
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; CHECK-LABEL: @sub_ashr_and_i64(
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; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i64 [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: [[AND:%.*]] = select i1 [[TMP1]], i64 [[X]], i64 0
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; CHECK-NEXT: ret i64 [[AND]]
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;
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%sub = sub nsw i64 %y, %x
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%shr = ashr i64 %sub, 63
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%and = and i64 %shr, %x
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ret i64 %and
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}
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; nuw nsw
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define i32 @sub_ashr_and_i32_nuw_nsw(i32 %x, i32 %y) {
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; CHECK-LABEL: @sub_ashr_and_i32_nuw_nsw(
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; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: [[AND:%.*]] = select i1 [[TMP1]], i32 [[X]], i32 0
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; CHECK-NEXT: ret i32 [[AND]]
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;
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%sub = sub nuw nsw i32 %y, %x
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%shr = ashr i32 %sub, 31
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%and = and i32 %shr, %x
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ret i32 %and
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}
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; Commute
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define i32 @sub_ashr_and_i32_commute(i32 %x, i32 %y) {
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; CHECK-LABEL: @sub_ashr_and_i32_commute(
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; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: [[AND:%.*]] = select i1 [[TMP1]], i32 [[X]], i32 0
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; CHECK-NEXT: ret i32 [[AND]]
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;
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%sub = sub nsw i32 %y, %x
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%shr = ashr i32 %sub, 31
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%and = and i32 %x, %shr ; commute %x and %shr
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ret i32 %and
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}
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; Vector Types
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define <4 x i32> @sub_ashr_and_i32_vec(<4 x i32> %x, <4 x i32> %y) {
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; CHECK-LABEL: @sub_ashr_and_i32_vec(
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; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt <4 x i32> [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: [[AND:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> [[X]], <4 x i32> zeroinitializer
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; CHECK-NEXT: ret <4 x i32> [[AND]]
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;
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%sub = sub nsw <4 x i32> %y, %x
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%shr = ashr <4 x i32> %sub, <i32 31, i32 31, i32 31, i32 31>
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%and = and <4 x i32> %shr, %x
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ret <4 x i32> %and
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}
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define <4 x i32> @sub_ashr_and_i32_vec_nuw_nsw(<4 x i32> %x, <4 x i32> %y) {
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; CHECK-LABEL: @sub_ashr_and_i32_vec_nuw_nsw(
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; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt <4 x i32> [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: [[AND:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> [[X]], <4 x i32> zeroinitializer
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; CHECK-NEXT: ret <4 x i32> [[AND]]
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;
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%sub = sub nuw nsw <4 x i32> %y, %x
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%shr = ashr <4 x i32> %sub, <i32 31, i32 31, i32 31, i32 31>
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%and = and <4 x i32> %shr, %x
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ret <4 x i32> %and
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}
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define <4 x i32> @sub_ashr_and_i32_vec_commute(<4 x i32> %x, <4 x i32> %y) {
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; CHECK-LABEL: @sub_ashr_and_i32_vec_commute(
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; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt <4 x i32> [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: [[AND:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> [[X]], <4 x i32> zeroinitializer
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; CHECK-NEXT: ret <4 x i32> [[AND]]
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;
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%sub = sub nsw <4 x i32> %y, %x
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%shr = ashr <4 x i32> %sub, <i32 31, i32 31, i32 31, i32 31>
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%and = and <4 x i32> %x, %shr ; commute %x and %shr
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ret <4 x i32> %and
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}
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; Extra uses
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define i32 @sub_ashr_and_i32_extra_use_sub(i32 %x, i32 %y, i32* %p) {
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; CHECK-LABEL: @sub_ashr_and_i32_extra_use_sub(
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; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[Y:%.*]], [[X:%.*]]
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; CHECK-NEXT: store i32 [[SUB]], i32* [[P:%.*]], align 4
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; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[Y]], [[X]]
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; CHECK-NEXT: [[AND:%.*]] = select i1 [[TMP1]], i32 [[X]], i32 0
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; CHECK-NEXT: ret i32 [[AND]]
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;
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%sub = sub nsw i32 %y, %x
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store i32 %sub, i32* %p
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%shr = ashr i32 %sub, 31
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%and = and i32 %shr, %x
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ret i32 %and
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}
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define i32 @sub_ashr_and_i32_extra_use_and(i32 %x, i32 %y, i32* %p) {
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; CHECK-LABEL: @sub_ashr_and_i32_extra_use_and(
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; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: [[AND:%.*]] = select i1 [[TMP1]], i32 [[X]], i32 0
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; CHECK-NEXT: store i32 [[AND]], i32* [[P:%.*]], align 4
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; CHECK-NEXT: ret i32 [[AND]]
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;
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%sub = sub nsw i32 %y, %x
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%shr = ashr i32 %sub, 31
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%and = and i32 %shr, %x
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store i32 %and, i32* %p
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ret i32 %and
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}
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; Negative Tests
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define i32 @sub_ashr_and_i32_extra_use_ashr(i32 %x, i32 %y, i32* %p) {
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; CHECK-LABEL: @sub_ashr_and_i32_extra_use_ashr(
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; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[Y:%.*]], [[X:%.*]]
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; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 31
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; CHECK-NEXT: store i32 [[SHR]], i32* [[P:%.*]], align 4
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; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHR]], [[X]]
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; CHECK-NEXT: ret i32 [[AND]]
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;
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%sub = sub nsw i32 %y, %x
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%shr = ashr i32 %sub, 31
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store i32 %shr, i32* %p
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%and = and i32 %shr, %x
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ret i32 %and
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}
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define i32 @sub_ashr_and_i32_no_nuw_nsw(i32 %x, i32 %y) {
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; CHECK-LABEL: @sub_ashr_and_i32_no_nuw_nsw(
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; CHECK-NEXT: [[SUB:%.*]] = sub i32 [[Y:%.*]], [[X:%.*]]
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; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 7
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; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHR]], [[X]]
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; CHECK-NEXT: ret i32 [[AND]]
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;
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%sub = sub i32 %y, %x
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%shr = ashr i32 %sub, 7
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%and = and i32 %shr, %x
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ret i32 %and
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}
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define <4 x i32> @sub_ashr_and_i32_vec_undef(<4 x i32> %x, <4 x i32> %y) {
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; CHECK-LABEL: @sub_ashr_and_i32_vec_undef(
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; CHECK-NEXT: [[SUB:%.*]] = sub nsw <4 x i32> [[Y:%.*]], [[X:%.*]]
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; CHECK-NEXT: [[SHR:%.*]] = ashr <4 x i32> [[SUB]], <i32 31, i32 31, i32 31, i32 undef>
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; CHECK-NEXT: [[AND:%.*]] = and <4 x i32> [[SHR]], [[X]]
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; CHECK-NEXT: ret <4 x i32> [[AND]]
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;
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%sub = sub nsw <4 x i32> %y, %x
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%shr = ashr <4 x i32> %sub, <i32 31, i32 31, i32 31, i32 undef>
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%and = and <4 x i32> %shr, %x
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ret <4 x i32> %and
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}
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define i32 @sub_ashr_and_i32_shift_wrong_bit(i32 %x, i32 %y) {
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; CHECK-LABEL: @sub_ashr_and_i32_shift_wrong_bit(
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; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[Y:%.*]], [[X:%.*]]
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; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 15
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; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHR]], [[X]]
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; CHECK-NEXT: ret i32 [[AND]]
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;
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%sub = sub nsw i32 %y, %x
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%shr = ashr i32 %sub, 15
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%and = and i32 %shr, %x
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ret i32 %and
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}
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