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https://github.com/RPCS3/llvm-mirror.git
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2f13163a84
This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
73 lines
2.1 KiB
LLVM
73 lines
2.1 KiB
LLVM
; RUN: llc -mtriple=arm64-none-linux-gnu -code-model=large < %s | FileCheck %s
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@var8 = global i8 0
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@var16 = global i16 0
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@var32 = global i32 0
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@var64 = global i64 0
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define i8* @global_addr() {
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; CHECK-LABEL: global_addr:
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ret i8* @var8
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; The movz/movk calculation should end up returned directly in x0.
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; CHECK: movz x0, #:abs_g3:var8
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; CHECK: movk x0, #:abs_g2_nc:var8
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; CHECK: movk x0, #:abs_g1_nc:var8
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; CHECK: movk x0, #:abs_g0_nc:var8
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; CHECK-NEXT: ret
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}
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define i8 @global_i8() {
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; CHECK-LABEL: global_i8:
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%val = load i8* @var8
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ret i8 %val
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; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var8
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; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var8
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; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var8
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; CHECK: movk x[[ADDR_REG]], #:abs_g0_nc:var8
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; CHECK: ldrb w0, [x[[ADDR_REG]]]
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}
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define i16 @global_i16() {
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; CHECK-LABEL: global_i16:
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%val = load i16* @var16
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ret i16 %val
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; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var16
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; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var16
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; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var16
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; CHECK: movk x[[ADDR_REG]], #:abs_g0_nc:var16
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; CHECK: ldrh w0, [x[[ADDR_REG]]]
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}
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define i32 @global_i32() {
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; CHECK-LABEL: global_i32:
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%val = load i32* @var32
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ret i32 %val
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; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var32
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; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var32
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; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var32
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; CHECK: movk x[[ADDR_REG]], #:abs_g0_nc:var32
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; CHECK: ldr w0, [x[[ADDR_REG]]]
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}
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define i64 @global_i64() {
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; CHECK-LABEL: global_i64:
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%val = load i64* @var64
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ret i64 %val
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; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var64
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; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var64
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; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var64
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; CHECK: movk x[[ADDR_REG]], #:abs_g0_nc:var64
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; CHECK: ldr x0, [x[[ADDR_REG]]]
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}
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define <2 x i64> @constpool() {
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; CHECK-LABEL: constpool:
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ret <2 x i64> <i64 123456789, i64 987654321100>
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; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:[[CPADDR:.LCPI[0-9]+_[0-9]+]]
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; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:[[CPADDR]]
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; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:[[CPADDR]]
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; CHECK: movk x[[ADDR_REG]], #:abs_g0_nc:[[CPADDR]]
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; CHECK: ldr q0, [x[[ADDR_REG]]]
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}
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