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7184969f04
Summary: extract_vector_elt can cause an implicit any_ext if the types don't match. When processing the following pattern: (and (extract_vector_elt (load ([non_ext|any_ext|zero_ext] V))), c) DAGCombine was ignoring the possible extend, and sometimes removing the AND even though it was required to maintain some of the bits in the result to 0, resulting in a miscompile. This change fixes the issue by limiting the transformation only to cases where the extract_vector_elt doesn't perform the implicit extend. Reviewers: t.p.northover, jmolloy Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D18247 llvm-svn: 263935
67 lines
1.9 KiB
LLVM
67 lines
1.9 KiB
LLVM
; RUN: llc -mtriple armv7 %s -o - | FileCheck %s
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; CHECK-LABEL: f:
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define float @f(<4 x i16>* nocapture %in) {
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; CHECK: vld1
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; CHECK: vmovl.u16
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; CHECK-NOT: vand
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%1 = load <4 x i16>, <4 x i16>* %in
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; CHECK: vcvt.f32.u32
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%2 = uitofp <4 x i16> %1 to <4 x float>
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%3 = extractelement <4 x float> %2, i32 0
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%4 = extractelement <4 x float> %2, i32 1
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%5 = extractelement <4 x float> %2, i32 2
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; CHECK: vadd.f32
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%6 = fadd float %3, %4
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%7 = fadd float %6, %5
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ret float %7
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}
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; CHECK-LABEL: g:
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define float @g(<4 x i16>* nocapture %in) {
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; CHECK: vldr
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%1 = load <4 x i16>, <4 x i16>* %in
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; For now we're generating a vmov.16 and a uxth instruction.
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; The uxth is redundant, and we should be able to extend without
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; having to generate cross-domain copies. Once we can do this
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; we should modify the checks below.
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; CHECK: uxth
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%2 = extractelement <4 x i16> %1, i32 0
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; CHECK: vcvt.f32.u32
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%3 = uitofp i16 %2 to float
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ret float %3
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}
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; The backend generates for the following code an
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; (and 0xff (i32 extract_vector_elt (zext load <4 x i8> to 4 x i16)))
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;
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; The and is not redundant and cannot be removed. Since
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; extract_vector_elt is doing an implicit any_ext, the and
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; is required to guarantee that the top bits are set to zero.
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; Ideally should be a zext from <4 x i8> to <4 x 32>.
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; CHECK-LABEL: h:
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; CHECK: vld1.32
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; CHECK: uxtb
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define <4 x i32> @h(<4 x i8> *%in) {
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%1 = load <4 x i8>, <4 x i8>* %in, align 4
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%2 = extractelement <4 x i8> %1, i32 0
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%3 = zext i8 %2 to i32
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%4 = insertelement <4 x i32> undef, i32 %3, i32 0
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%5 = extractelement <4 x i8> %1, i32 1
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%6 = zext i8 %5 to i32
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%7 = insertelement <4 x i32> %4, i32 %6, i32 1
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%8 = extractelement <4 x i8> %1, i32 2
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%9 = zext i8 %8 to i32
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%10 = insertelement <4 x i32> %7, i32 %9, i32 2
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%11 = extractelement <4 x i8> %1, i32 3
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%12 = zext i8 %11 to i32
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%13 = insertelement <4 x i32> %10, i32 %12, i32 3
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ret <4 x i32> %13
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}
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