Simon Tatham cd2724a625 [TableGen:AsmWriter] Cope with consecutive tied operands. ... When you define an instruction alias as a subclass of InstAlias, you specify all the MC operands for the instruction it expands to, except for operands that are tied to a previous one, which you leave out in the expectation that the Tablegen output code will fill them in automatically. But the code in Tablegen's AsmWriter backend that skips over a tied operand was doing it using 'if' instead of 'while', because it wasn't expecting to find two tied operands in sequence. So if an instruction updates a pair of registers in place, so that its MC representation has two input operands tied to the output ones (for example, Arm's UMLAL instruction), then any alias which wants to expand to a special case of that instruction is likely to fail to match, because the indices of subsequent operands will be off by one in the generated printAliasInstr function. This patch re-indents some existing code, so it's clearest when viewed as a diff with whitespace changes ignored. Reviewers: fhahn, rengolin, sdesmalen, atanasyan, asb, jholewinski, t.p.northover, kparzysz, craig.topper, stoklund Reviewed By: rengolin Subscribers: javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D53816 llvm-svn: 349141		2018-12-14 11:39:55 +00:00
..
AsmMatcherEmitter.cpp
AsmWriterEmitter.cpp	[TableGen:AsmWriter] Cope with consecutive tied operands.	2018-12-14 11:39:55 +00:00
AsmWriterInst.cpp
AsmWriterInst.h
Attributes.cpp
CallingConvEmitter.cpp
CMakeLists.txt
CodeEmitterGen.cpp
CodeGenDAGPatterns.cpp	[TableGen] Preserve order of output operands in DAGISelMatcherGen	2018-12-05 00:47:59 +00:00
CodeGenDAGPatterns.h	[TableGen] Preserve order of output operands in DAGISelMatcherGen	2018-12-05 00:47:59 +00:00
CodeGenHwModes.cpp
CodeGenHwModes.h
CodeGenInstruction.cpp	[ARM][MC] Move information about variadic register defs into tablegen	2018-12-03 10:32:42 +00:00
CodeGenInstruction.h	[ARM][MC] Move information about variadic register defs into tablegen	2018-12-03 10:32:42 +00:00
CodeGenIntrinsics.h
CodeGenMapTable.cpp
CodeGenRegisters.cpp
CodeGenRegisters.h
CodeGenSchedule.cpp
CodeGenSchedule.h
CodeGenTarget.cpp
CodeGenTarget.h
CTagsEmitter.cpp
DAGISelEmitter.cpp
DAGISelMatcher.cpp
DAGISelMatcher.h
DAGISelMatcherEmitter.cpp
DAGISelMatcherGen.cpp	[TableGen] Preserve order of output operands in DAGISelMatcherGen	2018-12-05 00:47:59 +00:00
DAGISelMatcherOpt.cpp
DFAPacketizerEmitter.cpp
DisassemblerEmitter.cpp
ExegesisEmitter.cpp
FastISelEmitter.cpp
FixedLenDecoderEmitter.cpp	Recommit r349041: [tblgen][disasm] Separate encodings from instructions	2018-12-13 16:17:54 +00:00
GlobalISelEmitter.cpp
InfoByHwMode.cpp
InfoByHwMode.h
InstrDocsEmitter.cpp	[ARM][MC] Move information about variadic register defs into tablegen	2018-12-03 10:32:42 +00:00
InstrInfoEmitter.cpp	[TableGen] Improve the formatting of the emitted predicates (NFC)	2018-12-04 01:43:22 +00:00
IntrinsicEmitter.cpp
LLVMBuild.txt
OptParserEmitter.cpp
PredicateExpander.cpp	[TableGen] Fix negation of simple predicates	2018-11-30 21:03:24 +00:00
PredicateExpander.h
PseudoLoweringEmitter.cpp
RegisterBankEmitter.cpp
RegisterInfoEmitter.cpp
RISCVCompressInstEmitter.cpp
SDNodeProperties.cpp
SDNodeProperties.h
SearchableTableEmitter.cpp
SequenceToOffsetTable.h
SubtargetEmitter.cpp
SubtargetFeatureInfo.cpp
SubtargetFeatureInfo.h
TableGen.cpp
TableGenBackends.h
tdtags
Types.cpp
Types.h
WebAssemblyDisassemblerEmitter.cpp
WebAssemblyDisassemblerEmitter.h
X86DisassemblerShared.h
X86DisassemblerTables.cpp
X86DisassemblerTables.h
X86EVEX2VEXTablesEmitter.cpp
X86FoldTablesEmitter.cpp
X86ModRMFilters.cpp
X86ModRMFilters.h
X86RecognizableInstr.cpp
X86RecognizableInstr.h