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ead0e16c6e
This patch does the following: * Fix FIXME on `needsStackRealignment`: it is now shared between multiple targets, implemented in `TargetRegisterInfo`, and isn't `virtual` anymore. This will break out-of-tree targets, silently if they used `virtual` and with a build error if they used `override`. * Factor out `canRealignStack` as a `virtual` function on `TargetRegisterInfo`, by default only looks for the `no-realign-stack` function attribute. Multiple targets duplicated the same `needsStackRealignment` code: - Aarch64. - ARM. - Mips almost: had extra `DEBUG` diagnostic, which the default implementation now has. - PowerPC. - WebAssembly. - x86 almost: has an extra `-force-align-stack` option, which the default implementation now has. The default implementation of `needsStackRealignment` used to just return `false`. My current patch changes the behavior by simply using the above shared behavior. This affects: - AMDGPU - BPF - CppBackend - MSP430 - NVPTX - Sparc - SystemZ - XCore - Out-of-tree targets This is a breaking change! `make check` passes. The only implementation of the `virtual` function (besides the slight different in x86) was Hexagon (which did `MF.getFrameInfo()->getMaxAlignment() > 8`), and potentially some out-of-tree targets. Hexagon now uses the default implementation. `needsStackRealignment` was being overwritten in `<Target>GenRegisterInfo.inc`, to return `false` as the default also did. That was odd and is now gone. Reviewers: sunfish Subscribers: aemerson, llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11160 llvm-svn: 242727
319 lines
10 KiB
C++
319 lines
10 KiB
C++
//===-- MipsRegisterInfo.cpp - MIPS Register Information -== --------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the MIPS implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "MipsRegisterInfo.h"
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#include "Mips.h"
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#include "MipsAnalyzeImmediate.h"
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#include "MipsInstrInfo.h"
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#include "MipsMachineFunction.h"
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#include "MipsSubtarget.h"
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#include "MipsTargetMachine.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/IR/DebugInfo.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/Type.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetFrameLowering.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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#define DEBUG_TYPE "mips-reg-info"
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#define GET_REGINFO_TARGET_DESC
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#include "MipsGenRegisterInfo.inc"
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MipsRegisterInfo::MipsRegisterInfo() : MipsGenRegisterInfo(Mips::RA) {}
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unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
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const TargetRegisterClass *
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MipsRegisterInfo::getPointerRegClass(const MachineFunction &MF,
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unsigned Kind) const {
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MipsABIInfo ABI = MF.getSubtarget<MipsSubtarget>().getABI();
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return ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
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}
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unsigned
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MipsRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
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MachineFunction &MF) const {
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switch (RC->getID()) {
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default:
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return 0;
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case Mips::GPR32RegClassID:
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case Mips::GPR64RegClassID:
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case Mips::DSPRRegClassID: {
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const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
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return 28 - TFI->hasFP(MF);
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}
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case Mips::FGR32RegClassID:
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return 32;
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case Mips::AFGR64RegClassID:
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return 16;
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case Mips::FGR64RegClassID:
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return 32;
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}
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}
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//===----------------------------------------------------------------------===//
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// Callee Saved Registers methods
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//===----------------------------------------------------------------------===//
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/// Mips Callee Saved Registers
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const MCPhysReg *
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MipsRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
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const MipsSubtarget &Subtarget = MF->getSubtarget<MipsSubtarget>();
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if (Subtarget.isSingleFloat())
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return CSR_SingleFloatOnly_SaveList;
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if (Subtarget.isABI_N64())
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return CSR_N64_SaveList;
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if (Subtarget.isABI_N32())
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return CSR_N32_SaveList;
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if (Subtarget.isFP64bit())
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return CSR_O32_FP64_SaveList;
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if (Subtarget.isFPXX())
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return CSR_O32_FPXX_SaveList;
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return CSR_O32_SaveList;
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}
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const uint32_t *
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MipsRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
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CallingConv::ID) const {
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const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
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if (Subtarget.isSingleFloat())
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return CSR_SingleFloatOnly_RegMask;
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if (Subtarget.isABI_N64())
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return CSR_N64_RegMask;
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if (Subtarget.isABI_N32())
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return CSR_N32_RegMask;
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if (Subtarget.isFP64bit())
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return CSR_O32_FP64_RegMask;
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if (Subtarget.isFPXX())
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return CSR_O32_FPXX_RegMask;
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return CSR_O32_RegMask;
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}
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const uint32_t *MipsRegisterInfo::getMips16RetHelperMask() {
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return CSR_Mips16RetHelper_RegMask;
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}
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BitVector MipsRegisterInfo::
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getReservedRegs(const MachineFunction &MF) const {
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static const MCPhysReg ReservedGPR32[] = {
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Mips::ZERO, Mips::K0, Mips::K1, Mips::SP
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};
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static const MCPhysReg ReservedGPR64[] = {
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Mips::ZERO_64, Mips::K0_64, Mips::K1_64, Mips::SP_64
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};
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BitVector Reserved(getNumRegs());
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const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
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typedef TargetRegisterClass::const_iterator RegIter;
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for (unsigned I = 0; I < array_lengthof(ReservedGPR32); ++I)
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Reserved.set(ReservedGPR32[I]);
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// Reserve registers for the NaCl sandbox.
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if (Subtarget.isTargetNaCl()) {
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Reserved.set(Mips::T6); // Reserved for control flow mask.
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Reserved.set(Mips::T7); // Reserved for memory access mask.
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Reserved.set(Mips::T8); // Reserved for thread pointer.
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}
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for (unsigned I = 0; I < array_lengthof(ReservedGPR64); ++I)
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Reserved.set(ReservedGPR64[I]);
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// For mno-abicalls, GP is a program invariant!
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if (!Subtarget.isABICalls()) {
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Reserved.set(Mips::GP);
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Reserved.set(Mips::GP_64);
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}
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if (Subtarget.isFP64bit()) {
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// Reserve all registers in AFGR64.
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for (RegIter Reg = Mips::AFGR64RegClass.begin(),
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EReg = Mips::AFGR64RegClass.end(); Reg != EReg; ++Reg)
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Reserved.set(*Reg);
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} else {
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// Reserve all registers in FGR64.
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for (RegIter Reg = Mips::FGR64RegClass.begin(),
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EReg = Mips::FGR64RegClass.end(); Reg != EReg; ++Reg)
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Reserved.set(*Reg);
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}
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// Reserve FP if this function should have a dedicated frame pointer register.
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if (Subtarget.getFrameLowering()->hasFP(MF)) {
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if (Subtarget.inMips16Mode())
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Reserved.set(Mips::S0);
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else {
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Reserved.set(Mips::FP);
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Reserved.set(Mips::FP_64);
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// Reserve the base register if we need to both realign the stack and
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// allocate variable-sized objects at runtime. This should test the
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// same conditions as MipsFrameLowering::hasBP().
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if (needsStackRealignment(MF) &&
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MF.getFrameInfo()->hasVarSizedObjects()) {
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Reserved.set(Mips::S7);
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Reserved.set(Mips::S7_64);
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}
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}
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}
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// Reserve hardware registers.
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Reserved.set(Mips::HWR29);
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// Reserve DSP control register.
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Reserved.set(Mips::DSPPos);
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Reserved.set(Mips::DSPSCount);
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Reserved.set(Mips::DSPCarry);
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Reserved.set(Mips::DSPEFI);
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Reserved.set(Mips::DSPOutFlag);
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// Reserve MSA control registers.
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Reserved.set(Mips::MSAIR);
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Reserved.set(Mips::MSACSR);
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Reserved.set(Mips::MSAAccess);
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Reserved.set(Mips::MSASave);
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Reserved.set(Mips::MSAModify);
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Reserved.set(Mips::MSARequest);
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Reserved.set(Mips::MSAMap);
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Reserved.set(Mips::MSAUnmap);
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// Reserve RA if in mips16 mode.
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if (Subtarget.inMips16Mode()) {
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const MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
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Reserved.set(Mips::RA);
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Reserved.set(Mips::RA_64);
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Reserved.set(Mips::T0);
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Reserved.set(Mips::T1);
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if (MF.getFunction()->hasFnAttribute("saveS2") || MipsFI->hasSaveS2())
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Reserved.set(Mips::S2);
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}
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// Reserve GP if small section is used.
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if (Subtarget.useSmallSection()) {
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Reserved.set(Mips::GP);
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Reserved.set(Mips::GP_64);
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}
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if (Subtarget.isABI_O32() && !Subtarget.useOddSPReg()) {
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for (const auto &Reg : Mips::OddSPRegClass)
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Reserved.set(Reg);
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}
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return Reserved;
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}
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bool
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MipsRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
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return true;
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}
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bool
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MipsRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
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return true;
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}
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// FrameIndex represent objects inside a abstract stack.
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// We must replace FrameIndex with an stack/frame pointer
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// direct reference.
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void MipsRegisterInfo::
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eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
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unsigned FIOperandNum, RegScavenger *RS) const {
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MachineInstr &MI = *II;
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MachineFunction &MF = *MI.getParent()->getParent();
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DEBUG(errs() << "\nFunction : " << MF.getName() << "\n";
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errs() << "<--------->\n" << MI);
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int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
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uint64_t stackSize = MF.getFrameInfo()->getStackSize();
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int64_t spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
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DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"
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<< "spOffset : " << spOffset << "\n"
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<< "stackSize : " << stackSize << "\n");
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eliminateFI(MI, FIOperandNum, FrameIndex, stackSize, spOffset);
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}
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unsigned MipsRegisterInfo::
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getFrameRegister(const MachineFunction &MF) const {
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const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
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const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
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bool IsN64 =
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static_cast<const MipsTargetMachine &>(MF.getTarget()).getABI().IsN64();
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if (Subtarget.inMips16Mode())
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return TFI->hasFP(MF) ? Mips::S0 : Mips::SP;
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else
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return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) :
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(IsN64 ? Mips::SP_64 : Mips::SP);
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}
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bool MipsRegisterInfo::canRealignStack(const MachineFunction &MF) const {
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// Avoid realigning functions that explicitly do not want to be realigned.
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// Normally, we should report an error when a function should be dynamically
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// realigned but also has the attribute no-realign-stack. Unfortunately,
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// with this attribute, MachineFrameInfo clamps each new object's alignment
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// to that of the stack's alignment as specified by the ABI. As a result,
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// the information of whether we have objects with larger alignment
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// requirement than the stack's alignment is already lost at this point.
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if (!TargetRegisterInfo::canRealignStack(MF))
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return false;
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const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
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unsigned FP = Subtarget.isGP32bit() ? Mips::FP : Mips::FP_64;
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unsigned BP = Subtarget.isGP32bit() ? Mips::S7 : Mips::S7_64;
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// Support dynamic stack realignment only for targets with standard encoding.
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if (!Subtarget.hasStandardEncoding())
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return false;
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// We can't perform dynamic stack realignment if we can't reserve the
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// frame pointer register.
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if (!MF.getRegInfo().canReserveReg(FP))
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return false;
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// We can realign the stack if we know the maximum call frame size and we
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// don't have variable sized objects.
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if (Subtarget.getFrameLowering()->hasReservedCallFrame(MF))
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return true;
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// We have to reserve the base pointer register in the presence of variable
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// sized objects.
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return MF.getRegInfo().canReserveReg(BP);
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}
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