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5eefec9e6d
Previously we modelled VPR128 and VPR64 as essentially identical register-classes containing V0-V31 (which had Q0-Q31 as "sub_alias" sub-registers). This model is starting to cause significant problems for code generation, particularly writing EXTRACT/INSERT_SUBREG patterns for converting between the two. The change here switches to classifying VPR64 & VPR128 as RegisterOperands, which are essentially aliases for RegisterClasses with different parsing and printing behaviour. This fits almost exactly with their real status (VPR128 == FPR128 printed strangely, VPR64 == FPR64 printed strangely). llvm-svn: 190665
210 lines
9.6 KiB
ArmAsm
210 lines
9.6 KiB
ArmAsm
// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
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// Check that the assembler can handle the documented syntax for AArch64
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//----------------------------------------------------------------------
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// Vector Move Immediate Shifted
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//----------------------------------------------------------------------
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movi v0.2s, #1
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movi v1.2s, #0
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movi v15.2s, #1, lsl #8
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movi v16.2s, #1, lsl #16
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movi v31.2s, #1, lsl #24
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movi v0.4s, #1
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movi v0.4s, #1, lsl #8
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movi v0.4s, #1, lsl #16
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movi v0.4s, #1, lsl #24
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movi v0.4h, #1
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movi v0.4h, #1, lsl #8
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movi v0.8h, #1
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movi v0.8h, #1, lsl #8
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// CHECK: movi v0.2s, #0x1 // encoding: [0x20,0x04,0x00,0x0f]
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// CHECK: movi v1.2s, #0x0 // encoding: [0x01,0x04,0x00,0x0f]
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// CHECK: movi v15.2s, #0x1, lsl #8 // encoding: [0x2f,0x24,0x00,0x0f]
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// CHECK: movi v16.2s, #0x1, lsl #16 // encoding: [0x30,0x44,0x00,0x0f]
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// CHECK: movi v31.2s, #0x1, lsl #24 // encoding: [0x3f,0x64,0x00,0x0f]
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// CHECK: movi v0.4s, #0x1 // encoding: [0x20,0x04,0x00,0x4f]
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// CHECK: movi v0.4s, #0x1, lsl #8 // encoding: [0x20,0x24,0x00,0x4f]
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// CHECK: movi v0.4s, #0x1, lsl #16 // encoding: [0x20,0x44,0x00,0x4f]
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// CHECK: movi v0.4s, #0x1, lsl #24 // encoding: [0x20,0x64,0x00,0x4f]
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// CHECK: movi v0.4h, #0x1 // encoding: [0x20,0x84,0x00,0x0f]
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// CHECK: movi v0.4h, #0x1, lsl #8 // encoding: [0x20,0xa4,0x00,0x0f]
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// CHECK: movi v0.8h, #0x1 // encoding: [0x20,0x84,0x00,0x4f]
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// CHECK: movi v0.8h, #0x1, lsl #8 // encoding: [0x20,0xa4,0x00,0x4f]
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//----------------------------------------------------------------------
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// Vector Move Inverted Immediate Shifted
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//----------------------------------------------------------------------
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mvni v0.2s, #1
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mvni v1.2s, #0
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mvni v0.2s, #1, lsl #8
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mvni v0.2s, #1, lsl #16
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mvni v0.2s, #1, lsl #24
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mvni v0.4s, #1
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mvni v15.4s, #1, lsl #8
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mvni v16.4s, #1, lsl #16
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mvni v31.4s, #1, lsl #24
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mvni v0.4h, #1
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mvni v0.4h, #1, lsl #8
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mvni v0.8h, #1
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mvni v0.8h, #1, lsl #8
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// CHECK: mvni v0.2s, #0x1 // encoding: [0x20,0x04,0x00,0x2f]
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// CHECK: mvni v1.2s, #0x0 // encoding: [0x01,0x04,0x00,0x2f]
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// CHECK: mvni v0.2s, #0x1, lsl #8 // encoding: [0x20,0x24,0x00,0x2f]
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// CHECK: mvni v0.2s, #0x1, lsl #16 // encoding: [0x20,0x44,0x00,0x2f]
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// CHECK: mvni v0.2s, #0x1, lsl #24 // encoding: [0x20,0x64,0x00,0x2f]
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// CHECK: mvni v0.4s, #0x1 // encoding: [0x20,0x04,0x00,0x6f]
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// CHECK: mvni v15.4s, #0x1, lsl #8 // encoding: [0x2f,0x24,0x00,0x6f]
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// CHECK: mvni v16.4s, #0x1, lsl #16 // encoding: [0x30,0x44,0x00,0x6f]
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// CHECK: mvni v31.4s, #0x1, lsl #24 // encoding: [0x3f,0x64,0x00,0x6f]
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// CHECK: mvni v0.4h, #0x1 // encoding: [0x20,0x84,0x00,0x2f]
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// CHECK: mvni v0.4h, #0x1, lsl #8 // encoding: [0x20,0xa4,0x00,0x2f]
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// CHECK: mvni v0.8h, #0x1 // encoding: [0x20,0x84,0x00,0x6f]
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// CHECK: mvni v0.8h, #0x1, lsl #8 // encoding: [0x20,0xa4,0x00,0x6f]
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//----------------------------------------------------------------------
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// Vector Bitwise Bit Clear (AND NOT) - immediate
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//----------------------------------------------------------------------
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bic v0.2s, #1
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bic v1.2s, #0
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bic v0.2s, #1, lsl #8
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bic v0.2s, #1, lsl #16
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bic v0.2s, #1, lsl #24
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bic v0.4s, #1
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bic v0.4s, #1, lsl #8
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bic v0.4s, #1, lsl #16
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bic v0.4s, #1, lsl #24
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bic v15.4h, #1
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bic v16.4h, #1, lsl #8
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bic v0.8h, #1
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bic v31.8h, #1, lsl #8
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// CHECK: bic v0.2s, #0x1 // encoding: [0x20,0x14,0x00,0x2f]
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// CHECK: bic v1.2s, #0x0 // encoding: [0x01,0x14,0x00,0x2f]
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// CHECK: bic v0.2s, #0x1, lsl #8 // encoding: [0x20,0x34,0x00,0x2f]
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// CHECK: bic v0.2s, #0x1, lsl #16 // encoding: [0x20,0x54,0x00,0x2f]
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// CHECK: bic v0.2s, #0x1, lsl #24 // encoding: [0x20,0x74,0x00,0x2f]
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// CHECK: bic v0.4s, #0x1 // encoding: [0x20,0x14,0x00,0x6f]
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// CHECK: bic v0.4s, #0x1, lsl #8 // encoding: [0x20,0x34,0x00,0x6f]
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// CHECK: bic v0.4s, #0x1, lsl #16 // encoding: [0x20,0x54,0x00,0x6f]
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// CHECK: bic v0.4s, #0x1, lsl #24 // encoding: [0x20,0x74,0x00,0x6f]
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// CHECK: bic v15.4h, #0x1 // encoding: [0x2f,0x94,0x00,0x2f]
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// CHECK: bic v16.4h, #0x1, lsl #8 // encoding: [0x30,0xb4,0x00,0x2f]
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// CHECK: bic v0.8h, #0x1 // encoding: [0x20,0x94,0x00,0x6f]
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// CHECK: bic v31.8h, #0x1, lsl #8 // encoding: [0x3f,0xb4,0x00,0x6f]
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//----------------------------------------------------------------------
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// Vector Bitwise OR - immedidate
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//----------------------------------------------------------------------
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orr v0.2s, #1
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orr v1.2s, #0
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orr v0.2s, #1, lsl #8
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orr v0.2s, #1, lsl #16
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orr v0.2s, #1, lsl #24
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orr v0.4s, #1
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orr v0.4s, #1, lsl #8
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orr v0.4s, #1, lsl #16
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orr v0.4s, #1, lsl #24
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orr v31.4h, #1
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orr v15.4h, #1, lsl #8
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orr v0.8h, #1
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orr v16.8h, #1, lsl #8
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// CHECK: orr v0.2s, #0x1 // encoding: [0x20,0x14,0x00,0x0f]
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// CHECK: orr v1.2s, #0x0 // encoding: [0x01,0x14,0x00,0x0f]
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// CHECK: orr v0.2s, #0x1, lsl #8 // encoding: [0x20,0x34,0x00,0x0f]
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// CHECK: orr v0.2s, #0x1, lsl #16 // encoding: [0x20,0x54,0x00,0x0f]
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// CHECK: orr v0.2s, #0x1, lsl #24 // encoding: [0x20,0x74,0x00,0x0f]
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// CHECK: orr v0.4s, #0x1 // encoding: [0x20,0x14,0x00,0x4f]
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// CHECK: orr v0.4s, #0x1, lsl #8 // encoding: [0x20,0x34,0x00,0x4f]
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// CHECK: orr v0.4s, #0x1, lsl #16 // encoding: [0x20,0x54,0x00,0x4f]
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// CHECK: orr v0.4s, #0x1, lsl #24 // encoding: [0x20,0x74,0x00,0x4f]
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// CHECK: orr v31.4h, #0x1 // encoding: [0x3f,0x94,0x00,0x0f]
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// CHECK: orr v15.4h, #0x1, lsl #8 // encoding: [0x2f,0xb4,0x00,0x0f]
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// CHECK: orr v0.8h, #0x1 // encoding: [0x20,0x94,0x00,0x4f]
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// CHECK: orr v16.8h, #0x1, lsl #8 // encoding: [0x30,0xb4,0x00,0x4f]
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//----------------------------------------------------------------------
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// Vector Move Immediate Masked
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//----------------------------------------------------------------------
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movi v0.2s, #1, msl #8
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movi v1.2s, #1, msl #16
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movi v0.4s, #1, msl #8
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movi v31.4s, #1, msl #16
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// CHECK: movi v0.2s, #0x1, msl #8 // encoding: [0x20,0xc4,0x00,0x0f]
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// CHECK: movi v1.2s, #0x1, msl #16 // encoding: [0x21,0xd4,0x00,0x0f]
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// CHECK: movi v0.4s, #0x1, msl #8 // encoding: [0x20,0xc4,0x00,0x4f]
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// CHECK: movi v31.4s, #0x1, msl #16 // encoding: [0x3f,0xd4,0x00,0x4f]
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//----------------------------------------------------------------------
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// Vector Move Inverted Immediate Masked
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//----------------------------------------------------------------------
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mvni v1.2s, #0x1, msl #8
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mvni v0.2s, #0x1, msl #16
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mvni v31.4s, #0x1, msl #8
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mvni v0.4s, #0x1, msl #16
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// CHECK: mvni v1.2s, #0x1, msl #8 // encoding: [0x21,0xc4,0x00,0x2f]
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// CHECK: mvni v0.2s, #0x1, msl #16 // encoding: [0x20,0xd4,0x00,0x2f]
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// CHECK: mvni v31.4s, #0x1, msl #8 // encoding: [0x3f,0xc4,0x00,0x6f]
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// CHECK: mvni v0.4s, #0x1, msl #16 // encoding: [0x20,0xd4,0x00,0x6f]
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//----------------------------------------------------------------------
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// Vector Immediate - per byte
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//----------------------------------------------------------------------
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movi v0.8b, #0
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movi v31.8b, #0xff
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movi v15.16b, #0xf
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movi v31.16b, #0x1f
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// CHECK: movi v0.8b, #0x0 // encoding: [0x00,0xe4,0x00,0x0f]
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// CHECK: movi v31.8b, #0xff // encoding: [0xff,0xe7,0x07,0x0f]
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// CHECK: movi v15.16b, #0xf // encoding: [0xef,0xe5,0x00,0x4f]
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// CHECK: movi v31.16b, #0x1f // encoding: [0xff,0xe7,0x00,0x4f]
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//----------------------------------------------------------------------
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// Vector Move Immediate - bytemask, per doubleword
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//---------------------------------------------------------------------
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movi v0.2d, #0xff00ff00ff00ff00
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// CHECK: movi v0.2d, #0xff00ff00ff00ff00 // encoding: [0x40,0xe5,0x05,0x6f]
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//----------------------------------------------------------------------
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// Vector Move Immediate - bytemask, one doubleword
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//----------------------------------------------------------------------
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movi d0, #0xff00ff00ff00ff00
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// CHECK: movi d0, #0xff00ff00ff00ff00 // encoding: [0x40,0xe5,0x05,0x2f]
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//----------------------------------------------------------------------
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// Vector Floating Point Move Immediate
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//----------------------------------------------------------------------
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fmov v1.2s, #1.0
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fmov v15.4s, #1.0
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fmov v31.2d, #1.0
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// CHECK: fmov v1.2s, #1.00000000 // encoding: [0x01,0xf6,0x03,0x0f]
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// CHECK: fmov v15.4s, #1.00000000 // encoding: [0x0f,0xf6,0x03,0x4f]
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// CHECK: fmov v31.2d, #1.00000000 // encoding: [0x1f,0xf6,0x03,0x6f]
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//----------------------------------------------------------------------
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// Vector Move - register
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//----------------------------------------------------------------------
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// FIXME: these should all print with the "mov" syntax.
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mov v0.8b, v31.8b
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mov v15.16b, v16.16b
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orr v0.8b, v31.8b, v31.8b
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orr v15.16b, v16.16b, v16.16b
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// CHECK: orr v0.8b, v31.8b, v31.8b // encoding: [0xe0,0x1f,0xbf,0x0e]
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// CHECK: orr v15.16b, v16.16b, v16.16b // encoding: [0x0f,0x1e,0xb0,0x4e]
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// CHECK: orr v0.8b, v31.8b, v31.8b // encoding: [0xe0,0x1f,0xbf,0x0e]
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// CHECK: orr v15.16b, v16.16b, v16.16b // encoding: [0x0f,0x1e,0xb0,0x4e]
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