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eb66331216
Currently, variadic operands on an MCInst are assumed to be uses, because they come after the defs. However, this is not always the case, for example the Arm/Thumb LDM instructions write to a variable number of registers. This adds a property of instruction definitions which can be used to mark variadic operands as defs. This only affects MCInst, because MachineInstruction already tracks use/def per operand in each instance of the instruction, so can already represent this. This property can then be checked in MCInstrDesc, allowing us to remove some special cases in ARMAsmParser::isITBlockTerminator. Differential revision: https://reviews.llvm.org/D54853 llvm-svn: 348114
67 lines
2.3 KiB
C++
67 lines
2.3 KiB
C++
//===------ llvm/MC/MCInstrDesc.cpp- Instruction Descriptors --------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines methods on the MCOperandInfo and MCInstrDesc classes, which
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// are used to describe target instructions and their operands.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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using namespace llvm;
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bool MCInstrDesc::getDeprecatedInfo(MCInst &MI, const MCSubtargetInfo &STI,
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std::string &Info) const {
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if (ComplexDeprecationInfo)
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return ComplexDeprecationInfo(MI, STI, Info);
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if (DeprecatedFeature != -1 && STI.getFeatureBits()[DeprecatedFeature]) {
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// FIXME: it would be nice to include the subtarget feature here.
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Info = "deprecated";
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return true;
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}
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return false;
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}
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bool MCInstrDesc::mayAffectControlFlow(const MCInst &MI,
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const MCRegisterInfo &RI) const {
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if (isBranch() || isCall() || isReturn() || isIndirectBranch())
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return true;
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unsigned PC = RI.getProgramCounter();
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if (PC == 0)
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return false;
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if (hasDefOfPhysReg(MI, PC, RI))
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return true;
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return false;
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}
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bool MCInstrDesc::hasImplicitDefOfPhysReg(unsigned Reg,
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const MCRegisterInfo *MRI) const {
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if (const MCPhysReg *ImpDefs = ImplicitDefs)
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for (; *ImpDefs; ++ImpDefs)
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if (*ImpDefs == Reg || (MRI && MRI->isSubRegister(Reg, *ImpDefs)))
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return true;
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return false;
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}
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bool MCInstrDesc::hasDefOfPhysReg(const MCInst &MI, unsigned Reg,
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const MCRegisterInfo &RI) const {
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for (int i = 0, e = NumDefs; i != e; ++i)
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if (MI.getOperand(i).isReg() &&
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RI.isSubRegisterEq(Reg, MI.getOperand(i).getReg()))
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return true;
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if (variadicOpsAreDefs())
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for (int i = NumOperands - 1, e = MI.getNumOperands(); i != e; ++i)
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if (MI.getOperand(i).isReg() &&
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RI.isSubRegisterEq(Reg, MI.getOperand(i).getReg()))
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return true;
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return hasImplicitDefOfPhysReg(Reg, &RI);
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}
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