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421ddae8b6
ARMv8.2-A adds 16-bit floating point versions of all existing SIMD floating-point instructions. This is an optional extension, so all of these instructions require the FeatureFullFP16 subtarget feature. Note that VFP without SIMD is not a valid combination for any version of ARMv8-A, but I have ensured that these instructions all depend on both FeatureNEON and FeatureFullFP16 for consistency. The ".2h" vector type specifier is now legal (for the scalar pairwise reduction instructions), so some unrelated tests have been modified as different error messages are emitted. This is not a problem as the invalid operands are still caught. llvm-svn: 255010
22 lines
864 B
ArmAsm
22 lines
864 B
ArmAsm
// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon,+fullfp16 -show-encoding < %s | FileCheck %s
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//----------------------------------------------------------------------
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// Scalar Reduce Add Pairwise (Integer)
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//----------------------------------------------------------------------
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addp d0, v1.2d
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// CHECK: addp d0, v1.2d // encoding: [0x20,0xb8,0xf1,0x5e]
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//----------------------------------------------------------------------
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// Scalar Reduce Add Pairwise (Floating Point)
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//----------------------------------------------------------------------
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faddp h18, v3.2h
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faddp h18, v3.2H
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faddp s19, v2.2s
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faddp d20, v1.2d
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// CHECK: faddp h18, v3.2h // encoding: [0x72,0xd8,0x30,0x5e]
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// CHECK: faddp s19, v2.2s // encoding: [0x53,0xd8,0x30,0x7e]
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// CHECK: faddp d20, v1.2d // encoding: [0x34,0xd8,0x70,0x7e]
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