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bbccd10c81
This adds diagnostic strings for the ARM floating-point register classes, which will be used when these classes are expected by the assembler, but the provided operand is not valid. One of these, DPR, requires C++ code to select the correct error message, as that class contains different registers depending on the FPU. The rest can all have their diagnostic strings stored in the tablegen decription of them. Differential revision: https://reviews.llvm.org/D36693 llvm-svn: 315304
78 lines
3.2 KiB
ArmAsm
78 lines
3.2 KiB
ArmAsm
@ RUN: not llvm-mc -triple=armv7-linux-gnueabi %s 2>&1 | FileCheck %s
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.text
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vorr.i32 d2, #0xffffffff
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vorr.i32 q2, #0xffffffff
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vorr.i32 d2, #0xabababab
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vorr.i32 q2, #0xabababab
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vorr.i16 q2, #0xabab
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vorr.i16 q2, #0xabab
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@ CHECK: error: invalid instruction, any one of the following would fix this:
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@ CHECK: operand must be a register in range [d0, d31]
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@ CHECK: note: invalid operand for instruction
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@ CHECK: vorr.i32 d2, #0xffffffff
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@ CHECK: error: invalid instruction, any one of the following would fix this:
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@ CHECK: note: operand must be a register in range [q0, q15]
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@ CHECK: note: invalid operand for instruction
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@ CHECK: vorr.i32 q2, #0xffffffff
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@ CHECK: error: invalid instruction, any one of the following would fix this:
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@ CHECK: operand must be a register in range [d0, d31]
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@ CHECK: note: invalid operand for instruction
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@ CHECK: vorr.i32 d2, #0xabababab
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@ CHECK: error: invalid instruction, any one of the following would fix this:
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@ CHECK: note: operand must be a register in range [q0, q15]
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@ CHECK: note: invalid operand for instruction
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@ CHECK: vorr.i32 q2, #0xabababab
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@ CHECK: error: invalid instruction, any one of the following would fix this:
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@ CHECK: note: operand must be a register in range [q0, q15]
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@ CHECK: note: invalid operand for instruction
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@ CHECK: vorr.i16 q2, #0xabab
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@ CHECK: error: invalid instruction, any one of the following would fix this:
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@ CHECK: note: operand must be a register in range [q0, q15]
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@ CHECK: note: invalid operand for instruction
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@ CHECK: vorr.i16 q2, #0xabab
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vbic.i32 d2, #0xffffffff
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vbic.i32 q2, #0xffffffff
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vbic.i32 d2, #0xabababab
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vbic.i32 q2, #0xabababab
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vbic.i16 d2, #0xabab
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vbic.i16 q2, #0xabab
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@ CHECK: error: invalid operand for instruction
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@ CHECK: vbic.i32 d2, #0xffffffff
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@ CHECK: error: invalid operand for instruction
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@ CHECK: vbic.i32 q2, #0xffffffff
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@ CHECK: error: invalid operand for instruction
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@ CHECK: vbic.i32 d2, #0xabababab
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@ CHECK: error: invalid operand for instruction
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@ CHECK: vbic.i32 q2, #0xabababab
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@ CHECK: error: invalid operand for instruction
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@ CHECK: vbic.i16 d2, #0xabab
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@ CHECK: error: invalid operand for instruction
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@ CHECK: vbic.i16 q2, #0xabab
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vbic.i32 d2, #0x03ffffff
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vbic.i32 q2, #0x03ffff
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vbic.i32 d2, #0x03ff
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vbic.i32 d2, #0xff00ff
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vbic.i16 d2, #0x03ff
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vbic.i16 q2, #0xf0f0
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vbic.i16 q2, #0xf0f0f0
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@ CHECK: error: invalid operand for instruction
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@ CHECK: vbic.i32 d2, #0x03ffffff
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@ CHECK: error: invalid operand for instruction
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@ CHECK: vbic.i32 q2, #0x03ffff
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@ CHECK: error: invalid operand for instruction
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@ CHECK: vbic.i32 d2, #0x03ff
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@ CHECK: error: invalid operand for instruction
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@ CHECK: vbic.i32 d2, #0xff00ff
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@ CHECK: error: invalid operand for instruction
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@ CHECK: vbic.i16 d2, #0x03ff
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@ CHECK: error: invalid operand for instruction
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@ CHECK: vbic.i16 q2, #0xf0f0
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@ CHECK: error: invalid operand for instruction
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@ CHECK: vbic.i16 q2, #0xf0f0f0
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