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64680cd5b8
The SPU ABI does not mention v64, and all examples in C suggest v128 are treated similarily to arrays, we use array alignment for v64 too. This makes the alignment of e.g. [2 x <2 x i32>] behave "intuitively" and similar to as if the elements were e.g. i32s. This also makes an "unaligned store" test to be aligned, with different (but functionally equivalent) code generated. llvm-svn: 117360
78 lines
1.6 KiB
LLVM
78 lines
1.6 KiB
LLVM
;RUN: llc --march=cellspu %s -o - | FileCheck %s
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%vec = type <2 x i32>
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define %vec @test_ret(%vec %param)
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{
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;CHECK: bi $lr
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ret %vec %param
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}
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define %vec @test_add(%vec %param)
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{
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;CHECK: a {{\$.}}, $3, $3
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%1 = add %vec %param, %param
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;CHECK: bi $lr
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ret %vec %1
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}
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define %vec @test_sub(%vec %param)
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{
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;CHECK: sf {{\$.}}, $4, $3
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%1 = sub %vec %param, <i32 1, i32 1>
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;CHECK: bi $lr
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ret %vec %1
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}
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define %vec @test_mul(%vec %param)
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{
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;CHECK: mpyu
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;CHECK: mpyh
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;CHECK: a {{\$., \$., \$.}}
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;CHECK: a {{\$., \$., \$.}}
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%1 = mul %vec %param, %param
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;CHECK: bi $lr
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ret %vec %1
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}
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define <2 x i32> @test_splat(i32 %param ) {
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;see svn log for why this is here...
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;CHECK-NOT: or $3, $3, $3
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;CHECK: lqa
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;CHECK: shufb
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%sv = insertelement <1 x i32> undef, i32 %param, i32 0
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%rv = shufflevector <1 x i32> %sv, <1 x i32> undef, <2 x i32> zeroinitializer
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;CHECK: bi $lr
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ret <2 x i32> %rv
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}
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define i32 @test_extract() {
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;CHECK: shufb $3
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%rv = extractelement <2 x i32> zeroinitializer, i32 undef ; <i32> [#uses=1]
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;CHECK: bi $lr
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ret i32 %rv
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}
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define void @test_store( %vec %val, %vec* %ptr)
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{
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;CHECK: stqd $3, 0(${{.}})
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;CHECK: bi $lr
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store %vec %val, %vec* %ptr
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ret void
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}
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;Alignment of <2 x i32> is not *directly* defined in the ABI
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;It probably is safe to interpret it as an array, thus having 8 byte
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;alignment (according to ABI). This tests that the size of
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;[2 x <2 x i32>] is 16 bytes, i.e. there is no padding between the
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;two arrays
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define <2 x i32>* @test_alignment( [2 x <2 x i32>]* %ptr)
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{
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; CHECK-NOT: ai $3, $3, 16
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; CHECK: ai $3, $3, 8
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; CHECK: bi $lr
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%rv = getelementptr [2 x <2 x i32>]* %ptr, i32 0, i32 1
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ret <2 x i32>* %rv
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}
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