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ebd26ebcfa
signed multiplication is requested. While there is not a difference in the *low* half of the result, the *high* half (used specifically to implement the signed division by these constants) certainly is used. The test case I've nuked was actively asserting wrong code. There is a delightful solution to doing signed multiplication even when we don't have it that Richard Smith has crafted, but I'll add the machinery back and implement that in a follow-up patch. This at least restores correctness. llvm-svn: 214007
217 lines
4.4 KiB
LLVM
217 lines
4.4 KiB
LLVM
; RUN: llc -march=x86-64 -mcpu=core2 -mattr=+sse4.1 < %s | FileCheck %s -check-prefix=SSE41
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; RUN: llc -march=x86-64 -mcpu=core2 < %s | FileCheck %s -check-prefix=SSE
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; RUN: llc -march=x86-64 -mcpu=core-avx2 < %s | FileCheck %s -check-prefix=AVX
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define <4 x i32> @test1(<4 x i32> %a) {
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%div = udiv <4 x i32> %a, <i32 7, i32 7, i32 7, i32 7>
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ret <4 x i32> %div
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; SSE41-LABEL: test1:
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; SSE41: pmuludq
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; SSE41: pshufd $49
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; SSE41: pmuludq
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; SSE41: shufps $-35
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; SSE41: psubd
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; SSE41: psrld $1
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; SSE41: padd
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; SSE41: psrld $2
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; AVX-LABEL: test1:
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; AVX: vpmuludq
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; AVX: vpshufd $49
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; AVX: vpmuludq
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; AVX: vshufps $-35
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; AVX: vpsubd
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; AVX: vpsrld $1
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; AVX: vpadd
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; AVX: vpsrld $2
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}
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define <8 x i32> @test2(<8 x i32> %a) {
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%div = udiv <8 x i32> %a, <i32 7, i32 7, i32 7, i32 7,i32 7, i32 7, i32 7, i32 7>
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ret <8 x i32> %div
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; AVX-LABEL: test2:
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; AVX: vpbroadcastd
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; AVX: vpalignr $4
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; AVX: vpmuludq
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; AVX: vpmuludq
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; AVX: vpblendd $170
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; AVX: vpsubd
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; AVX: vpsrld $1
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; AVX: vpadd
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; AVX: vpsrld $2
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}
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define <8 x i16> @test3(<8 x i16> %a) {
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%div = udiv <8 x i16> %a, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
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ret <8 x i16> %div
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; SSE41-LABEL: test3:
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; SSE41: pmulhuw
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; SSE41: psubw
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; SSE41: psrlw $1
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; SSE41: paddw
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; SSE41: psrlw $2
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; AVX-LABEL: test3:
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; AVX: vpmulhuw
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; AVX: vpsubw
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; AVX: vpsrlw $1
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; AVX: vpaddw
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; AVX: vpsrlw $2
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}
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define <16 x i16> @test4(<16 x i16> %a) {
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%div = udiv <16 x i16> %a, <i16 7, i16 7, i16 7, i16 7,i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7,i16 7, i16 7, i16 7, i16 7>
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ret <16 x i16> %div
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; AVX-LABEL: test4:
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; AVX: vpmulhuw
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; AVX: vpsubw
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; AVX: vpsrlw $1
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; AVX: vpaddw
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; AVX: vpsrlw $2
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; AVX-NOT: vpmulhuw
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}
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define <8 x i16> @test5(<8 x i16> %a) {
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%div = sdiv <8 x i16> %a, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
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ret <8 x i16> %div
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; SSE41-LABEL: test5:
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; SSE41: pmulhw
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; SSE41: psrlw $15
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; SSE41: psraw $1
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; SSE41: paddw
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; AVX-LABEL: test5:
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; AVX: vpmulhw
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; AVX: vpsrlw $15
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; AVX: vpsraw $1
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; AVX: vpaddw
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}
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define <16 x i16> @test6(<16 x i16> %a) {
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%div = sdiv <16 x i16> %a, <i16 7, i16 7, i16 7, i16 7,i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7,i16 7, i16 7, i16 7, i16 7>
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ret <16 x i16> %div
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; AVX-LABEL: test6:
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; AVX: vpmulhw
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; AVX: vpsrlw $15
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; AVX: vpsraw $1
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; AVX: vpaddw
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; AVX-NOT: vpmulhw
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}
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define <16 x i8> @test7(<16 x i8> %a) {
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%div = sdiv <16 x i8> %a, <i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7>
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ret <16 x i8> %div
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; FIXME: scalarized
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; SSE41-LABEL: test7:
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; SSE41: pext
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; AVX-LABEL: test7:
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; AVX: pext
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}
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define <4 x i32> @test8(<4 x i32> %a) {
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%div = sdiv <4 x i32> %a, <i32 7, i32 7, i32 7, i32 7>
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ret <4 x i32> %div
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; SSE41-LABEL: test8:
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; SSE41: pmuldq
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; SSE41: pshufd $49
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; SSE41: pshufd $49
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; SSE41: pmuldq
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; SSE41: shufps $-35
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; SSE41: pshufd $-40
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; SSE41: padd
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; SSE41: psrld $31
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; SSE41: psrad $2
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; SSE41: padd
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; FIXME: scalarized -- there is no signed multiply in SSE.
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; SSE-LABEL: test8:
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; SSE: imulq
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; SSE: imulq
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; SSE: imulq
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; SSE: imulq
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; AVX-LABEL: test8:
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; AVX: vpmuldq
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; AVX: vpshufd $49
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; AVX: vpshufd $49
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; AVX: vpmuldq
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; AVX: vshufps $-35
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; AVX: vpshufd $-40
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; AVX: vpadd
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; AVX: vpsrld $31
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; AVX: vpsrad $2
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; AVX: vpadd
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}
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define <8 x i32> @test9(<8 x i32> %a) {
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%div = sdiv <8 x i32> %a, <i32 7, i32 7, i32 7, i32 7,i32 7, i32 7, i32 7, i32 7>
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ret <8 x i32> %div
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; AVX-LABEL: test9:
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; AVX: vpbroadcastd
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; AVX: vpalignr $4
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; AVX: vpalignr $4
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; AVX: vpmuldq
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; AVX: vpmuldq
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; AVX: vpalignr $4
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; AVX: vpblendd $170
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; AVX: vpadd
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; AVX: vpsrld $31
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; AVX: vpsrad $2
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; AVX: vpadd
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}
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define <8 x i32> @test10(<8 x i32> %a) {
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%rem = urem <8 x i32> %a, <i32 7, i32 7, i32 7, i32 7,i32 7, i32 7, i32 7, i32 7>
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ret <8 x i32> %rem
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; AVX-LABEL: test10:
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; AVX: vpbroadcastd
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; AVX: vpalignr $4
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; AVX: vpmuludq
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; AVX: vpmuludq
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; AVX: vpblendd $170
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; AVX: vpsubd
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; AVX: vpsrld $1
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; AVX: vpadd
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; AVX: vpsrld $2
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; AVX: vpmulld
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}
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define <8 x i32> @test11(<8 x i32> %a) {
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%rem = srem <8 x i32> %a, <i32 7, i32 7, i32 7, i32 7,i32 7, i32 7, i32 7, i32 7>
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ret <8 x i32> %rem
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; AVX-LABEL: test11:
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; AVX: vpbroadcastd
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; AVX: vpalignr $4
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; AVX: vpalignr $4
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; AVX: vpmuldq
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; AVX: vpmuldq
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; AVX: vpalignr $4
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; AVX: vpblendd $170
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; AVX: vpadd
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; AVX: vpsrld $31
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; AVX: vpsrad $2
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; AVX: vpadd
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; AVX: vpmulld
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}
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define <2 x i16> @test12() {
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%I8 = insertelement <2 x i16> zeroinitializer, i16 -1, i32 0
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%I9 = insertelement <2 x i16> %I8, i16 -1, i32 1
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%B9 = urem <2 x i16> %I9, %I9
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ret <2 x i16> %B9
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; AVX-LABEL: test12:
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; AVX: xorps
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}
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