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https://github.com/RPCS3/llvm-mirror.git
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012d4e61ae
llvm-svn: 314049
248 lines
7.2 KiB
C++
248 lines
7.2 KiB
C++
//===- InterferenceCache.h - Caching per-block interference ----*- C++ -*--===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// InterferenceCache remembers per-block interference from LiveIntervalUnions,
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// fixed RegUnit interference, and register masks.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_CODEGEN_INTERFERENCECACHE_H
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#define LLVM_LIB_CODEGEN_INTERFERENCECACHE_H
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/LiveInterval.h"
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#include "llvm/CodeGen/LiveIntervalUnion.h"
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#include "llvm/CodeGen/SlotIndexes.h"
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#include "llvm/Support/Compiler.h"
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#include <cassert>
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#include <cstddef>
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#include <cstdlib>
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namespace llvm {
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class LiveIntervals;
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class MachineFunction;
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class TargetRegisterInfo;
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class LLVM_LIBRARY_VISIBILITY InterferenceCache {
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/// BlockInterference - information about the interference in a single basic
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/// block.
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struct BlockInterference {
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unsigned Tag = 0;
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SlotIndex First;
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SlotIndex Last;
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BlockInterference() {}
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};
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/// Entry - A cache entry containing interference information for all aliases
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/// of PhysReg in all basic blocks.
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class Entry {
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/// PhysReg - The register currently represented.
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unsigned PhysReg = 0;
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/// Tag - Cache tag is changed when any of the underlying LiveIntervalUnions
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/// change.
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unsigned Tag = 0;
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/// RefCount - The total number of Cursor instances referring to this Entry.
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unsigned RefCount = 0;
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/// MF - The current function.
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MachineFunction *MF;
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/// Indexes - Mapping block numbers to SlotIndex ranges.
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SlotIndexes *Indexes = nullptr;
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/// LIS - Used for accessing register mask interference maps.
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LiveIntervals *LIS = nullptr;
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/// PrevPos - The previous position the iterators were moved to.
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SlotIndex PrevPos;
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/// RegUnitInfo - Information tracked about each RegUnit in PhysReg.
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/// When PrevPos is set, the iterators are valid as if advanceTo(PrevPos)
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/// had just been called.
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struct RegUnitInfo {
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/// Iterator pointing into the LiveIntervalUnion containing virtual
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/// register interference.
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LiveIntervalUnion::SegmentIter VirtI;
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/// Tag of the LIU last time we looked.
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unsigned VirtTag;
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/// Fixed interference in RegUnit.
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LiveRange *Fixed = nullptr;
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/// Iterator pointing into the fixed RegUnit interference.
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LiveInterval::iterator FixedI;
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RegUnitInfo(LiveIntervalUnion &LIU) : VirtTag(LIU.getTag()) {
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VirtI.setMap(LIU.getMap());
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}
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};
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/// Info for each RegUnit in PhysReg. It is very rare ofr a PHysReg to have
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/// more than 4 RegUnits.
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SmallVector<RegUnitInfo, 4> RegUnits;
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/// Blocks - Interference for each block in the function.
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SmallVector<BlockInterference, 8> Blocks;
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/// update - Recompute Blocks[MBBNum]
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void update(unsigned MBBNum);
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public:
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Entry() = default;
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void clear(MachineFunction *mf, SlotIndexes *indexes, LiveIntervals *lis) {
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assert(!hasRefs() && "Cannot clear cache entry with references");
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PhysReg = 0;
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MF = mf;
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Indexes = indexes;
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LIS = lis;
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}
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unsigned getPhysReg() const { return PhysReg; }
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void addRef(int Delta) { RefCount += Delta; }
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bool hasRefs() const { return RefCount > 0; }
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void revalidate(LiveIntervalUnion *LIUArray, const TargetRegisterInfo *TRI);
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/// valid - Return true if this is a valid entry for physReg.
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bool valid(LiveIntervalUnion *LIUArray, const TargetRegisterInfo *TRI);
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/// reset - Initialize entry to represent physReg's aliases.
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void reset(unsigned physReg,
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LiveIntervalUnion *LIUArray,
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const TargetRegisterInfo *TRI,
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const MachineFunction *MF);
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/// get - Return an up to date BlockInterference.
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BlockInterference *get(unsigned MBBNum) {
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if (Blocks[MBBNum].Tag != Tag)
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update(MBBNum);
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return &Blocks[MBBNum];
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}
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};
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// We don't keep a cache entry for every physical register, that would use too
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// much memory. Instead, a fixed number of cache entries are used in a round-
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// robin manner.
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enum { CacheEntries = 32 };
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const TargetRegisterInfo *TRI = nullptr;
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LiveIntervalUnion *LIUArray = nullptr;
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MachineFunction *MF = nullptr;
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// Point to an entry for each physreg. The entry pointed to may not be up to
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// date, and it may have been reused for a different physreg.
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unsigned char* PhysRegEntries = nullptr;
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size_t PhysRegEntriesCount = 0;
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// Next round-robin entry to be picked.
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unsigned RoundRobin = 0;
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// The actual cache entries.
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Entry Entries[CacheEntries];
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// get - Get a valid entry for PhysReg.
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Entry *get(unsigned PhysReg);
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public:
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friend class Cursor;
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InterferenceCache() = default;
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~InterferenceCache() {
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free(PhysRegEntries);
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}
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void reinitPhysRegEntries();
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/// init - Prepare cache for a new function.
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void init(MachineFunction *mf, LiveIntervalUnion *liuarray,
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SlotIndexes *indexes, LiveIntervals *lis,
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const TargetRegisterInfo *tri);
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/// getMaxCursors - Return the maximum number of concurrent cursors that can
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/// be supported.
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unsigned getMaxCursors() const { return CacheEntries; }
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/// Cursor - The primary query interface for the block interference cache.
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class Cursor {
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Entry *CacheEntry = nullptr;
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const BlockInterference *Current = nullptr;
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static const BlockInterference NoInterference;
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void setEntry(Entry *E) {
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Current = nullptr;
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// Update reference counts. Nothing happens when RefCount reaches 0, so
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// we don't have to check for E == CacheEntry etc.
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if (CacheEntry)
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CacheEntry->addRef(-1);
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CacheEntry = E;
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if (CacheEntry)
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CacheEntry->addRef(+1);
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}
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public:
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/// Cursor - Create a dangling cursor.
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Cursor() = default;
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Cursor(const Cursor &O) {
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setEntry(O.CacheEntry);
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}
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Cursor &operator=(const Cursor &O) {
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setEntry(O.CacheEntry);
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return *this;
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}
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~Cursor() { setEntry(nullptr); }
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/// setPhysReg - Point this cursor to PhysReg's interference.
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void setPhysReg(InterferenceCache &Cache, unsigned PhysReg) {
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// Release reference before getting a new one. That guarantees we can
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// actually have CacheEntries live cursors.
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setEntry(nullptr);
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if (PhysReg)
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setEntry(Cache.get(PhysReg));
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}
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/// moveTo - Move cursor to basic block MBBNum.
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void moveToBlock(unsigned MBBNum) {
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Current = CacheEntry ? CacheEntry->get(MBBNum) : &NoInterference;
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}
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/// hasInterference - Return true if the current block has any interference.
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bool hasInterference() {
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return Current->First.isValid();
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}
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/// first - Return the starting index of the first interfering range in the
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/// current block.
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SlotIndex first() {
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return Current->First;
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}
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/// last - Return the ending index of the last interfering range in the
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/// current block.
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SlotIndex last() {
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return Current->Last;
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}
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};
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};
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} // end namespace llvm
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#endif // LLVM_LIB_CODEGEN_INTERFERENCECACHE_H
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