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356 lines
11 KiB
C++
356 lines
11 KiB
C++
//===------------------------- GCNRegPressure.cpp - -----------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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//
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//===----------------------------------------------------------------------===//
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#include "GCNRegPressure.h"
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using namespace llvm;
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#define DEBUG_TYPE "misched"
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#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
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LLVM_DUMP_METHOD
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void llvm::printLivesAt(SlotIndex SI,
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const LiveIntervals &LIS,
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const MachineRegisterInfo &MRI) {
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dbgs() << "Live regs at " << SI << ": "
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<< *LIS.getInstructionFromIndex(SI);
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unsigned Num = 0;
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for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
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const unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
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if (MRI.reg_nodbg_empty(Reg))
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continue;
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const auto &LI = LIS.getInterval(Reg);
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if (LI.hasSubRanges()) {
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bool firstTime = true;
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for (const auto &S : LI.subranges()) {
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if (!S.liveAt(SI)) continue;
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if (firstTime) {
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dbgs() << " " << PrintReg(Reg, MRI.getTargetRegisterInfo())
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<< '\n';
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firstTime = false;
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}
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dbgs() << " " << S << '\n';
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++Num;
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}
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} else if (LI.liveAt(SI)) {
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dbgs() << " " << LI << '\n';
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++Num;
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}
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}
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if (!Num) dbgs() << " <none>\n";
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}
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static bool isEqual(const GCNRPTracker::LiveRegSet &S1,
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const GCNRPTracker::LiveRegSet &S2) {
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if (S1.size() != S2.size())
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return false;
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for (const auto &P : S1) {
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auto I = S2.find(P.first);
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if (I == S2.end() || I->second != P.second)
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return false;
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}
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return true;
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}
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static GCNRPTracker::LiveRegSet
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stripEmpty(const GCNRPTracker::LiveRegSet &LR) {
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GCNRPTracker::LiveRegSet Res;
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for (const auto &P : LR) {
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if (P.second.any())
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Res.insert(P);
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}
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return Res;
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}
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#endif
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///////////////////////////////////////////////////////////////////////////////
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// GCNRegPressure
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unsigned GCNRegPressure::getRegKind(unsigned Reg,
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const MachineRegisterInfo &MRI) {
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assert(TargetRegisterInfo::isVirtualRegister(Reg));
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const auto RC = MRI.getRegClass(Reg);
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auto STI = static_cast<const SIRegisterInfo*>(MRI.getTargetRegisterInfo());
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return STI->isSGPRClass(RC) ?
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(RC->getSize() == 4 ? SGPR32 : SGPR_TUPLE) :
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(RC->getSize() == 4 ? VGPR32 : VGPR_TUPLE);
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}
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void GCNRegPressure::inc(unsigned Reg,
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LaneBitmask PrevMask,
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LaneBitmask NewMask,
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const MachineRegisterInfo &MRI) {
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if (NewMask == PrevMask)
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return;
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int Sign = 1;
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if (NewMask < PrevMask) {
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std::swap(NewMask, PrevMask);
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Sign = -1;
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}
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#ifndef NDEBUG
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const auto MaxMask = MRI.getMaxLaneMaskForVReg(Reg);
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#endif
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switch (auto Kind = getRegKind(Reg, MRI)) {
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case SGPR32:
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case VGPR32:
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assert(PrevMask.none() && NewMask == MaxMask);
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Value[Kind] += Sign;
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break;
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case SGPR_TUPLE:
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case VGPR_TUPLE:
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assert(NewMask < MaxMask || NewMask == MaxMask);
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assert(PrevMask < NewMask);
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Value[Kind == SGPR_TUPLE ? SGPR32 : VGPR32] +=
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Sign * countPopulation((~PrevMask & NewMask).getAsInteger());
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if (PrevMask.none()) {
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assert(NewMask.any());
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Value[Kind] += Sign * MRI.getPressureSets(Reg).getWeight();
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}
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break;
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default: llvm_unreachable("Unknown register kind");
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}
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}
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bool GCNRegPressure::less(const SISubtarget &ST,
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const GCNRegPressure& O,
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unsigned MaxOccupancy) const {
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const auto SGPROcc = std::min(MaxOccupancy,
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ST.getOccupancyWithNumSGPRs(getSGRPNum()));
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const auto VGPROcc = std::min(MaxOccupancy,
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ST.getOccupancyWithNumVGPRs(getVGRPNum()));
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const auto OtherSGPROcc = std::min(MaxOccupancy,
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ST.getOccupancyWithNumSGPRs(O.getSGRPNum()));
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const auto OtherVGPROcc = std::min(MaxOccupancy,
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ST.getOccupancyWithNumVGPRs(O.getVGRPNum()));
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const auto Occ = std::min(SGPROcc, VGPROcc);
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const auto OtherOcc = std::min(OtherSGPROcc, OtherVGPROcc);
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if (Occ != OtherOcc)
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return Occ > OtherOcc;
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bool SGPRImportant = SGPROcc < VGPROcc;
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const bool OtherSGPRImportant = OtherSGPROcc < OtherVGPROcc;
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// if both pressures disagree on what is more important compare vgprs
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if (SGPRImportant != OtherSGPRImportant) {
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SGPRImportant = false;
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}
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// compare large regs pressure
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bool SGPRFirst = SGPRImportant;
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for (int I = 2; I > 0; --I, SGPRFirst = !SGPRFirst) {
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if (SGPRFirst) {
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auto SW = getSGPRTuplesWeight();
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auto OtherSW = O.getSGPRTuplesWeight();
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if (SW != OtherSW)
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return SW < OtherSW;
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} else {
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auto VW = getVGPRTuplesWeight();
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auto OtherVW = O.getVGPRTuplesWeight();
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if (VW != OtherVW)
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return VW < OtherVW;
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}
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}
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return SGPRImportant ? (getSGRPNum() < O.getSGRPNum()):
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(getVGRPNum() < O.getVGRPNum());
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}
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#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
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LLVM_DUMP_METHOD
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void GCNRegPressure::print(raw_ostream &OS, const SISubtarget *ST) const {
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OS << "VGPRs: " << getVGRPNum();
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if (ST) OS << "(O" << ST->getOccupancyWithNumVGPRs(getVGRPNum()) << ')';
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OS << ", SGPRs: " << getSGRPNum();
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if (ST) OS << "(O" << ST->getOccupancyWithNumSGPRs(getSGRPNum()) << ')';
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OS << ", LVGPR WT: " << getVGPRTuplesWeight()
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<< ", LSGPR WT: " << getSGPRTuplesWeight();
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if (ST) OS << " -> Occ: " << getOccupancy(*ST);
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OS << '\n';
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}
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#endif
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///////////////////////////////////////////////////////////////////////////////
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// GCNRPTracker
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LaneBitmask llvm::getLiveLaneMask(unsigned Reg,
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SlotIndex SI,
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const LiveIntervals &LIS,
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const MachineRegisterInfo &MRI) {
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assert(!MRI.reg_nodbg_empty(Reg));
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LaneBitmask LiveMask;
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const auto &LI = LIS.getInterval(Reg);
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if (LI.hasSubRanges()) {
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for (const auto &S : LI.subranges())
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if (S.liveAt(SI)) {
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LiveMask |= S.LaneMask;
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assert(LiveMask < MRI.getMaxLaneMaskForVReg(Reg) ||
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LiveMask == MRI.getMaxLaneMaskForVReg(Reg));
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}
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} else if (LI.liveAt(SI)) {
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LiveMask = MRI.getMaxLaneMaskForVReg(Reg);
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}
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return LiveMask;
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}
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GCNRPTracker::LiveRegSet llvm::getLiveRegs(SlotIndex SI,
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const LiveIntervals &LIS,
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const MachineRegisterInfo &MRI) {
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GCNRPTracker::LiveRegSet LiveRegs;
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for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
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auto Reg = TargetRegisterInfo::index2VirtReg(I);
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if (MRI.reg_nodbg_empty(Reg))
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continue;
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auto LiveMask = getLiveLaneMask(Reg, SI, LIS, MRI);
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if (LiveMask.any())
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LiveRegs[Reg] = LiveMask;
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}
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return LiveRegs;
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}
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void GCNUpwardRPTracker::reset(const MachineInstr &MI) {
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MRI = &MI.getParent()->getParent()->getRegInfo();
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LiveRegs = getLiveRegsAfter(MI, LIS);
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MaxPressure = CurPressure = getRegPressure(*MRI, LiveRegs);
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}
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LaneBitmask GCNUpwardRPTracker::getDefRegMask(const MachineOperand &MO) const {
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assert(MO.isDef() && MO.isReg() &&
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TargetRegisterInfo::isVirtualRegister(MO.getReg()));
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// We don't rely on read-undef flag because in case of tentative schedule
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// tracking it isn't set correctly yet. This works correctly however since
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// use mask has been tracked before using LIS.
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return MO.getSubReg() == 0 ?
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MRI->getMaxLaneMaskForVReg(MO.getReg()) :
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MRI->getTargetRegisterInfo()->getSubRegIndexLaneMask(MO.getSubReg());
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}
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LaneBitmask GCNUpwardRPTracker::getUsedRegMask(const MachineOperand &MO) const {
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assert(MO.isUse() && MO.isReg() &&
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TargetRegisterInfo::isVirtualRegister(MO.getReg()));
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if (auto SubReg = MO.getSubReg())
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return MRI->getTargetRegisterInfo()->getSubRegIndexLaneMask(SubReg);
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auto MaxMask = MRI->getMaxLaneMaskForVReg(MO.getReg());
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if (MaxMask.getAsInteger() == 1) // cannot have subregs
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return MaxMask;
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// For a tentative schedule LIS isn't updated yet but livemask should remain
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// the same on any schedule. Subreg defs can be reordered but they all must
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// dominate uses anyway.
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auto SI = LIS.getInstructionIndex(*MO.getParent()).getBaseIndex();
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return getLiveLaneMask(MO.getReg(), SI, LIS, *MRI);
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}
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void GCNUpwardRPTracker::recede(const MachineInstr &MI) {
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assert(MRI && "call reset first");
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LastTrackedMI = &MI;
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if (MI.isDebugValue())
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return;
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// process all defs first to ensure early clobbers are handled correctly
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// iterating over operands() to catch implicit defs
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for (const auto &MO : MI.operands()) {
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if (!MO.isReg() || !MO.isDef() ||
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!TargetRegisterInfo::isVirtualRegister(MO.getReg()))
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continue;
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auto Reg = MO.getReg();
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auto &LiveMask = LiveRegs[Reg];
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auto PrevMask = LiveMask;
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LiveMask &= ~getDefRegMask(MO);
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CurPressure.inc(Reg, PrevMask, LiveMask, *MRI);
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}
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// then all uses
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for (const auto &MO : MI.uses()) {
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if (!MO.isReg() || !MO.readsReg() ||
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!TargetRegisterInfo::isVirtualRegister(MO.getReg()))
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continue;
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auto Reg = MO.getReg();
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auto &LiveMask = LiveRegs[Reg];
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auto PrevMask = LiveMask;
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LiveMask |= getUsedRegMask(MO);
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CurPressure.inc(Reg, PrevMask, LiveMask, *MRI);
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}
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MaxPressure = max(MaxPressure, CurPressure);
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}
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#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
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LLVM_DUMP_METHOD
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static void reportMismatch(const GCNRPTracker::LiveRegSet &LISLR,
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const GCNRPTracker::LiveRegSet &TrackedLR,
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const TargetRegisterInfo *TRI) {
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for (auto const &P : TrackedLR) {
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auto I = LISLR.find(P.first);
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if (I == LISLR.end()) {
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dbgs() << " " << PrintReg(P.first, TRI)
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<< ":L" << PrintLaneMask(P.second)
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<< " isn't found in LIS reported set\n";
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}
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else if (I->second != P.second) {
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dbgs() << " " << PrintReg(P.first, TRI)
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<< " masks doesn't match: LIS reported "
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<< PrintLaneMask(I->second)
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<< ", tracked "
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<< PrintLaneMask(P.second)
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<< '\n';
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}
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}
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for (auto const &P : LISLR) {
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auto I = TrackedLR.find(P.first);
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if (I == TrackedLR.end()) {
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dbgs() << " " << PrintReg(P.first, TRI)
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<< ":L" << PrintLaneMask(P.second)
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<< " isn't found in tracked set\n";
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}
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}
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}
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bool GCNUpwardRPTracker::isValid() const {
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const auto &SI = LIS.getInstructionIndex(*LastTrackedMI).getBaseIndex();
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const auto LISLR = llvm::getLiveRegs(SI, LIS, *MRI);
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const auto TrackedLR = stripEmpty(LiveRegs);
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if (!isEqual(LISLR, TrackedLR)) {
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dbgs() << "\nGCNUpwardRPTracker error: Tracked and"
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" LIS reported livesets mismatch:\n";
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printLivesAt(SI, LIS, *MRI);
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reportMismatch(LISLR, TrackedLR, MRI->getTargetRegisterInfo());
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return false;
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}
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auto LISPressure = getRegPressure(*MRI, LISLR);
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if (LISPressure != CurPressure) {
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dbgs() << "GCNUpwardRPTracker error: Pressure sets different\nTracked: ";
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CurPressure.print(dbgs());
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dbgs() << "LIS rpt: ";
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LISPressure.print(dbgs());
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return false;
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}
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return true;
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}
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#endif
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