Simon Pilgrim 785a9fa4f0 [X86][SSE] Added extra (mul x, (1 << c)) -> x << c style vector tests ... vXi64 will benefit more from lowering to shifts than multiplies llvm-svn: 284461		2016-10-18 09:29:13 +00:00
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AArch64	GlobalISel: support wider range of load/store sizes in AArch64.	2016-10-17 18:36:53 +00:00
AMDGPU	[AMDGPU] Mark .note section SHF_ALLOC so lld creates a segment for it	2016-10-17 22:40:15 +00:00
ARM	[ARM] Assign cost of scaling for Cortex-R52	2016-10-18 09:08:54 +00:00
AVR
BPF
Generic
Hexagon
Inputs
Lanai
Mips
MIR	AMDGPU/SI: Handle s_getreg hazard in GCNHazardRecognizer	2016-10-15 00:58:14 +00:00
MSP430
NVPTX
PowerPC	PowerPC: specify full triple to avoid different Darwin asm syntax.	2016-10-14 21:25:29 +00:00
SPARC
SystemZ
Thumb
Thumb2
WebAssembly
WinEH
X86	[X86][SSE] Added extra (mul x, (1 << c)) -> x << c style vector tests	2016-10-18 09:29:13 +00:00
XCore