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e3e67d4a0a
This changes the SelectionDAG scheduling preference to source order. Soon, the SelectionDAG scheduler can be bypassed saving a nice chunk of compile time. Performance differences that result from this change are often a consequence of register coalescing. The register coalescer is far from perfect. Bugs can be filed for deficiencies. On x86 SandyBridge/Haswell, the source order schedule is often preserved, particularly for small blocks. Register pressure is generally improved over the SD scheduler's ILP mode. However, we are still able to handle large blocks that require latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also attempts to discover the critical path in single-block loops and adjust heuristics accordingly. The MI scheduler relies on the new machine model. This is currently unimplemented for AVX, so we may not be generating the best code yet. Unit tests are updated so they don't depend on SD scheduling heuristics. llvm-svn: 192750
86 lines
2.8 KiB
LLVM
86 lines
2.8 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=core-avx-i -mattr=+rdrnd | FileCheck %s
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declare {i16, i32} @llvm.x86.rdrand.16()
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declare {i32, i32} @llvm.x86.rdrand.32()
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declare {i64, i32} @llvm.x86.rdrand.64()
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define i32 @_rdrand16_step(i16* %random_val) {
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%call = call {i16, i32} @llvm.x86.rdrand.16()
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%randval = extractvalue {i16, i32} %call, 0
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store i16 %randval, i16* %random_val
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%isvalid = extractvalue {i16, i32} %call, 1
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ret i32 %isvalid
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; CHECK-LABEL: _rdrand16_step:
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; CHECK: rdrandw %ax
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; CHECK: movzwl %ax, %ecx
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; CHECK: movl $1, %eax
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; CHECK: cmovael %ecx, %eax
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; CHECK: movw %cx, (%r[[A0:di|cx]])
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; CHECK: ret
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}
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define i32 @_rdrand32_step(i32* %random_val) {
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%call = call {i32, i32} @llvm.x86.rdrand.32()
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%randval = extractvalue {i32, i32} %call, 0
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store i32 %randval, i32* %random_val
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%isvalid = extractvalue {i32, i32} %call, 1
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ret i32 %isvalid
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; CHECK-LABEL: _rdrand32_step:
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; CHECK: rdrandl %e[[T0:[a-z]+]]
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; CHECK: movl $1, %eax
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; CHECK: cmovael %e[[T0]], %eax
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; CHECK: movl %e[[T0]], (%r[[A0]])
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; CHECK: ret
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}
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define i32 @_rdrand64_step(i64* %random_val) {
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%call = call {i64, i32} @llvm.x86.rdrand.64()
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%randval = extractvalue {i64, i32} %call, 0
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store i64 %randval, i64* %random_val
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%isvalid = extractvalue {i64, i32} %call, 1
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ret i32 %isvalid
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; CHECK-LABEL: _rdrand64_step:
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; CHECK: rdrandq %r[[T1:[a-z]+]]
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; CHECK: movl $1, %eax
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; CHECK: cmovael %e[[T1]], %eax
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; CHECK: movq %r[[T1]], (%r[[A0]])
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; CHECK: ret
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}
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; Check that MachineCSE doesn't eliminate duplicate rdrand instructions.
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define i32 @CSE() nounwind {
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%rand1 = tail call { i32, i32 } @llvm.x86.rdrand.32() nounwind
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%v1 = extractvalue { i32, i32 } %rand1, 0
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%rand2 = tail call { i32, i32 } @llvm.x86.rdrand.32() nounwind
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%v2 = extractvalue { i32, i32 } %rand2, 0
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%add = add i32 %v2, %v1
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ret i32 %add
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; CHECK-LABEL: CSE:
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; CHECK: rdrandl
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; CHECK: rdrandl
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}
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; Check that MachineLICM doesn't hoist rdrand instructions.
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define void @loop(i32* %p, i32 %n) nounwind {
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entry:
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%tobool1 = icmp eq i32 %n, 0
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br i1 %tobool1, label %while.end, label %while.body
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while.body: ; preds = %entry, %while.body
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%p.addr.03 = phi i32* [ %incdec.ptr, %while.body ], [ %p, %entry ]
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%n.addr.02 = phi i32 [ %dec, %while.body ], [ %n, %entry ]
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%dec = add nsw i32 %n.addr.02, -1
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%incdec.ptr = getelementptr inbounds i32* %p.addr.03, i64 1
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%rand = tail call { i32, i32 } @llvm.x86.rdrand.32() nounwind
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%v1 = extractvalue { i32, i32 } %rand, 0
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store i32 %v1, i32* %p.addr.03, align 4
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%tobool = icmp eq i32 %dec, 0
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br i1 %tobool, label %while.end, label %while.body
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while.end: ; preds = %while.body, %entry
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ret void
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; CHECK-LABEL: loop:
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; CHECK-NOT: rdrandl
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; CHECK: This Inner Loop Header: Depth=1
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; CHECK: rdrandl
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}
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