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1ff24a7406
The the following instructions: - LD/LWZ (expanded from sjLj pseudo-instructions) - LXVL/LXVLL vector loads - STXVL/STXVLL vector stores all require G8RC_NO0X class registers for RA. Differential Revision: https://reviews.llvm.org/D29289 Committed for Lei Huang llvm-svn: 293769
30 lines
1.0 KiB
LLVM
30 lines
1.0 KiB
LLVM
; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -verify-machineinstrs | FileCheck %s
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; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 -verify-machineinstrs | FileCheck %s
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; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -verify-machineinstrs | FileCheck %s
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target datalayout = "e-m:e-i64:64-n32:64"
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target triple = "powerpc64le-unknown-linux-gnu"
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; Function Attrs: noinline nounwind
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define void @_Z23BuiltinLongJmpFunc1_bufv() #0 {
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entry:
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call void @llvm.eh.sjlj.longjmp(i8* bitcast (void ()* @_Z23BuiltinLongJmpFunc1_bufv to i8*))
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unreachable
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; CHECK: @_Z23BuiltinLongJmpFunc1_bufv
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; CHECK: addis [[REG:[0-9]+]], 2, .LC0@toc@ha
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; CHECK: ld 31, 0([[REG]])
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; CHECK: ld [[REG2:[0-9]+]], 8([[REG]])
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; CHECK-DAG: ld 1, 16([[REG]])
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; CHECK-DAG: ld 30, 32([[REG]])
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; CHECK-DAG: ld 2, 24([[REG]])
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; CHECK-DAG: mtctr [[REG2]]
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; CHECK: bctr
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return: ; No predecessors!
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ret void
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}
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; Function Attrs: noreturn nounwind
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declare void @llvm.eh.sjlj.longjmp(i8*) #1
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