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llvm-mirror/test/MC/Disassembler/ARM
Kevin Enderby d64ba28e41 Fix ARM disassembly of VLD2 (single 2-element structure to all lanes)
instructions with writebacks. And add test a case for all opcodes handed by
DecodeVLD2DupInstruction() in ARMDisassembler.cpp .

llvm-svn: 154884
2012-04-17 00:49:27 +00:00
..
arm-tests.txt Added soft fail checks for the disassembler when decoding some corner cases of the STRD, STRH, LDRD, LDRH, LDRSH and LDRSB instructions on ARM. 2012-03-22 14:14:49 +00:00
basic-arm-instructions.txt
fp-encoding.txt
invalid-Bcc-thumb.txt
invalid-BFI-arm.txt
invalid-CPS2p-arm.txt
invalid-CPS3p-arm.txt
invalid-DMB-thumb.txt
invalid-DSB-arm.txt
invalid-IT-CBNZ-thumb.txt
invalid-IT-CC15.txt Change ARMInstPrinter::printPredicateOperand() so it will not abort if it 2012-03-01 22:13:02 +00:00
invalid-IT-thumb.txt
invalid-LDC-form-arm.txt
invalid-LDM-thumb.txt
invalid-LDR_POST-arm.txt
invalid-LDR_PRE-arm.txt
invalid-LDRB_POST-arm.txt
invalid-LDRD_PRE-thumb.txt
invalid-LDRrs-arm.txt
invalid-MCR-arm.txt
invalid-MOVr-arm.txt
invalid-MOVs-arm.txt
invalid-MOVs-LSL-arm.txt
invalid-MOVTi16-arm.txt
invalid-MSRi-arm.txt
invalid-RFEorLDMIA-arm.txt
invalid-SBFX-arm.txt
invalid-SMLAD-arm.txt
invalid-SRS-arm.txt
invalid-STMIA_UPD-thumb.txt
invalid-SXTB-arm.txt
invalid-t2Bcc-thumb.txt
invalid-t2LDRBT-thumb.txt
invalid-t2LDREXD-thumb.txt
invalid-t2LDRSHi8-thumb.txt
invalid-t2LDRSHi12-thumb.txt
invalid-t2PUSH-thumb.txt
invalid-t2STR_POST-thumb.txt
invalid-t2STRD_PRE-thumb.txt
invalid-t2STREXB-thumb.txt
invalid-t2STREXD-thumb.txt
invalid-UMAAL-arm.txt
invalid-VLD1DUPq8_UPD-arm.txt
invalid-VLD3DUPd32_UPD-thumb.txt
invalid-VLDMSDB_UPD-arm.txt
invalid-VQADD-arm.txt
invalid-VST1d8Twb_register-thumb.txt Fixed a case of ARM disassembly getting an assert on a bad encoding 2012-04-11 22:40:17 +00:00
invalid-VST2b32_UPD-arm.txt
ldrd-armv4.txt Added fix in TableGen instruction decoder generation. The decoder now breaks for every leaf node. 2012-04-02 15:20:39 +00:00
lit.local.cfg Continue cleanup of LIT, getting rid of the remaining artifacts from dejagnu 2012-03-25 09:02:19 +00:00
memory-arm-instructions.txt
neon-tests.txt
neon.txt Fix ARM disassembly of VLD2 (single 2-element structure to all lanes) 2012-04-17 00:49:27 +00:00
neont2.txt Fix ARM disassembly of VLD2 (single 2-element structure to all lanes) 2012-04-17 00:49:27 +00:00
thumb1.txt
thumb2.txt
thumb-MSR-MClass.txt
thumb-printf.txt
thumb-tests.txt
unpredictable-ADC-arm.txt Added support for unpredictable ADC/SBC instructions on ARM, and also fixed some corner cases involving the PC register as an operand for these instructions. 2012-04-05 16:19:29 +00:00
unpredictable-ADDREXT3-arm.txt Added soft fail checks for the disassembler when decoding some corner cases of the STRD, STRH, LDRD, LDRH, LDRSH and LDRSB instructions on ARM. 2012-03-22 14:14:49 +00:00
unpredictable-LDR-arm.txt Added soft fail cases for the disassembler when decoding LDRSBT, LDRHT or LDRSHT instruction on ARM 2012-03-22 13:24:43 +00:00
unpredictable-LDRD-arm.txt Added soft fail checks for the disassembler when decoding some corner cases of the STRD, STRH, LDRD, LDRH, LDRSH and LDRSB instructions on ARM. 2012-03-22 14:14:49 +00:00
unpredictable-LSL-regform.txt The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this. 2012-03-20 15:54:56 +00:00
unpredictable-MUL-arm.txt Added soft fail cases for the disassembler when decoding MUL instructions on ARM. 2012-03-22 13:14:39 +00:00
unpredictable-RSC-arm.txt The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this. 2012-03-20 15:54:56 +00:00
unpredictable-SHADD16-arm.txt Added support for handling unpredictable arithmetic instructions on ARM. 2012-04-05 16:13:15 +00:00
unpredictable-SSAT-arm.txt The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this. 2012-03-20 15:54:56 +00:00
unpredictable-STRBrs-arm.txt The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this. 2012-03-20 15:54:56 +00:00
unpredictable-UQADD8-arm.txt The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this. 2012-03-20 15:54:56 +00:00
unpredictables-thumb.txt
vfp4.txt Fix a number of problems with ARM fused multiply add/subtract instructions. 2012-04-11 00:13:00 +00:00