mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-25 12:12:47 +01:00
1e20340b43
Summary: We rely on this in our CHERI backend to address the GOT by generating a $pc-relative addresses. For this we emit the following code sequence: lui $1, %pcrel_hi(_CHERI_CAPABILITY_TABLE_-8) daddiu $1, $1, %pcrel_lo(_CHERI_CAPABILITY_TABLE_-4) cgetpccincoffset $c1, $1 However, without this change the addend is implicitly converted to UINT32_MAX and an invalid pointer value is generated. Reviewers: atanasyan Reviewed By: atanasyan Subscribers: merge_guards_bot, sdardis, hiraditya, jrtc27, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70953
54 lines
1.8 KiB
C++
54 lines
1.8 KiB
C++
//===- MipsMCInstLower.h - Lower MachineInstr to MCInst --------*- C++ -*--===//
|
|
//
|
|
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
|
|
// See https://llvm.org/LICENSE.txt for license information.
|
|
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#ifndef LLVM_LIB_TARGET_MIPS_MIPSMCINSTLOWER_H
|
|
#define LLVM_LIB_TARGET_MIPS_MIPSMCINSTLOWER_H
|
|
|
|
#include "MCTargetDesc/MipsMCExpr.h"
|
|
#include "llvm/CodeGen/MachineOperand.h"
|
|
#include "llvm/Support/Compiler.h"
|
|
|
|
namespace llvm {
|
|
|
|
class MachineBasicBlock;
|
|
class MachineInstr;
|
|
class MCContext;
|
|
class MCInst;
|
|
class MCOperand;
|
|
class MipsAsmPrinter;
|
|
|
|
/// MipsMCInstLower - This class is used to lower an MachineInstr into an
|
|
/// MCInst.
|
|
class LLVM_LIBRARY_VISIBILITY MipsMCInstLower {
|
|
using MachineOperandType = MachineOperand::MachineOperandType;
|
|
|
|
MCContext *Ctx;
|
|
MipsAsmPrinter &AsmPrinter;
|
|
|
|
public:
|
|
MipsMCInstLower(MipsAsmPrinter &asmprinter);
|
|
|
|
void Initialize(MCContext *C);
|
|
void Lower(const MachineInstr *MI, MCInst &OutMI) const;
|
|
MCOperand LowerOperand(const MachineOperand &MO, int64_t offset = 0) const;
|
|
|
|
private:
|
|
MCOperand LowerSymbolOperand(const MachineOperand &MO,
|
|
MachineOperandType MOTy, int64_t Offset) const;
|
|
MCOperand createSub(MachineBasicBlock *BB1, MachineBasicBlock *BB2,
|
|
MipsMCExpr::MipsExprKind Kind) const;
|
|
void lowerLongBranchLUi(const MachineInstr *MI, MCInst &OutMI) const;
|
|
void lowerLongBranchADDiu(const MachineInstr *MI, MCInst &OutMI,
|
|
int Opcode) const;
|
|
bool lowerLongBranch(const MachineInstr *MI, MCInst &OutMI) const;
|
|
};
|
|
|
|
} // end namespace llvm
|
|
|
|
#endif // LLVM_LIB_TARGET_MIPS_MIPSMCINSTLOWER_H
|