Tom Stellard ecf6bd2eaa R600: Make sure to schedule AR register uses and defs in the same clause ... Reviewed-by: vljn at ovi.com llvm-svn: 183294		2013-06-05 03:43:06 +00:00
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AArch64	Change how we iterate over relocations on ELF.	2013-05-30 03:05:14 +00:00
ARM	Cortex-R5 can issue Thumb2 integer division instructions.	2013-06-04 22:52:09 +00:00
CPP	test commit: remove blank line.	2013-03-14 05:43:59 +00:00
Generic	Drop @llvm.annotation and @llvm.ptr.annotation intrinsics during codegen.	2013-05-21 14:37:16 +00:00
Hexagon	Hexagon: Pass to replace tranfer/copy instructions into combine instruction	2013-05-14 18:54:06 +00:00
Inputs	Revert "Adding DIImportedModules to DIScopes."	2013-03-28 02:44:59 +00:00
MBlaze	Remove unnecessary leading comment characters in lit-only file	2013-03-18 22:08:16 +00:00
Mips	[mips] Big-endian code generation for atomic instructions.	2013-05-31 03:25:44 +00:00
MSP430	DAGCombiner: Simplify inverted bit tests	2013-05-08 06:44:42 +00:00
NVPTX	[NVPTX] Re-enable support for virtual registers in the final output	2013-05-31 12:14:49 +00:00
PowerPC	Change how we iterate over relocations on ELF.	2013-05-30 03:05:14 +00:00
R600	R600: Make sure to schedule AR register uses and defs in the same clause	2013-06-05 03:43:06 +00:00
SI	Add R600 backend	2012-12-11 21:25:42 +00:00
SPARC	Sparc: Add support for indirect branch and blockaddress in Sparc backend.	2013-06-03 05:58:33 +00:00
SystemZ	[SystemZ] Don't use LOAD and STORE REVERSED for volatile accesses	2013-05-31 13:25:22 +00:00
Thumb	LocalStackSlotAllocation improvements	2013-04-30 20:04:37 +00:00
Thumb2	Cortex-R5 can issue Thumb2 integer division instructions.	2013-06-04 22:52:09 +00:00
X86	Revert r183069: "TMP: LEA64_32r fixing"	2013-06-01 10:23:46 +00:00
XCore	[XCore] Fix handling of functions where only the LR is spilled.	2013-05-09 16:43:42 +00:00