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af9e09671c
Summary: This is a follow up on https://reviews.llvm.org/D71473#inline-647262. There's a caveat here that `Align(1)` relies on the compiler understanding of `Log2_64` implementation to produce good code. One could use `Align()` as a replacement but I believe it is less clear that the alignment is one in that case. Reviewers: xbolva00, courbet, bollu Subscribers: arsenm, dylanmckay, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, jrtc27, atanasyan, jsji, Jim, kerbowa, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D73099
149 lines
5.2 KiB
C++
149 lines
5.2 KiB
C++
//===--- ARMBasicBlockInfo.cpp - Utilities for block sizes ---------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "ARMBasicBlockInfo.h"
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#include "ARM.h"
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#include "ARMBaseInstrInfo.h"
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#include "ARMMachineFunctionInfo.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/IR/GlobalVariable.h"
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#include "llvm/Support/Debug.h"
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#include <vector>
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#define DEBUG_TYPE "arm-bb-utils"
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using namespace llvm;
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namespace llvm {
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// mayOptimizeThumb2Instruction - Returns true if optimizeThumb2Instructions
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// below may shrink MI.
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static bool
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mayOptimizeThumb2Instruction(const MachineInstr *MI) {
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switch(MI->getOpcode()) {
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// optimizeThumb2Instructions.
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case ARM::t2LEApcrel:
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case ARM::t2LDRpci:
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// optimizeThumb2Branches.
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case ARM::t2B:
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case ARM::t2Bcc:
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case ARM::tBcc:
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// optimizeThumb2JumpTables.
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case ARM::t2BR_JT:
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case ARM::tBR_JTr:
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return true;
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}
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return false;
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}
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void ARMBasicBlockUtils::computeBlockSize(MachineBasicBlock *MBB) {
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LLVM_DEBUG(dbgs() << "computeBlockSize: " << MBB->getName() << "\n");
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BasicBlockInfo &BBI = BBInfo[MBB->getNumber()];
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BBI.Size = 0;
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BBI.Unalign = 0;
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BBI.PostAlign = Align(1);
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for (MachineInstr &I : *MBB) {
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BBI.Size += TII->getInstSizeInBytes(I);
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// For inline asm, getInstSizeInBytes returns a conservative estimate.
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// The actual size may be smaller, but still a multiple of the instr size.
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if (I.isInlineAsm())
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BBI.Unalign = isThumb ? 1 : 2;
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// Also consider instructions that may be shrunk later.
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else if (isThumb && mayOptimizeThumb2Instruction(&I))
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BBI.Unalign = 1;
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}
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// tBR_JTr contains a .align 2 directive.
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if (!MBB->empty() && MBB->back().getOpcode() == ARM::tBR_JTr) {
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BBI.PostAlign = Align(4);
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MBB->getParent()->ensureAlignment(Align(4));
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}
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}
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/// getOffsetOf - Return the current offset of the specified machine instruction
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/// from the start of the function. This offset changes as stuff is moved
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/// around inside the function.
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unsigned ARMBasicBlockUtils::getOffsetOf(MachineInstr *MI) const {
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const MachineBasicBlock *MBB = MI->getParent();
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// The offset is composed of two things: the sum of the sizes of all MBB's
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// before this instruction's block, and the offset from the start of the block
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// it is in.
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unsigned Offset = BBInfo[MBB->getNumber()].Offset;
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// Sum instructions before MI in MBB.
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for (MachineBasicBlock::const_iterator I = MBB->begin(); &*I != MI; ++I) {
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assert(I != MBB->end() && "Didn't find MI in its own basic block?");
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Offset += TII->getInstSizeInBytes(*I);
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}
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return Offset;
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}
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/// isBBInRange - Returns true if the distance between specific MI and
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/// specific BB can fit in MI's displacement field.
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bool ARMBasicBlockUtils::isBBInRange(MachineInstr *MI,
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MachineBasicBlock *DestBB,
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unsigned MaxDisp) const {
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unsigned PCAdj = isThumb ? 4 : 8;
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unsigned BrOffset = getOffsetOf(MI) + PCAdj;
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unsigned DestOffset = BBInfo[DestBB->getNumber()].Offset;
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LLVM_DEBUG(dbgs() << "Branch of destination " << printMBBReference(*DestBB)
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<< " from " << printMBBReference(*MI->getParent())
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<< " max delta=" << MaxDisp << " from " << getOffsetOf(MI)
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<< " to " << DestOffset << " offset "
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<< int(DestOffset - BrOffset) << "\t" << *MI);
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if (BrOffset <= DestOffset) {
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// Branch before the Dest.
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if (DestOffset-BrOffset <= MaxDisp)
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return true;
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} else {
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if (BrOffset-DestOffset <= MaxDisp)
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return true;
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}
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return false;
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}
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void ARMBasicBlockUtils::adjustBBOffsetsAfter(MachineBasicBlock *BB) {
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assert(BB->getParent() == &MF &&
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"Basic block is not a child of the current function.\n");
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unsigned BBNum = BB->getNumber();
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LLVM_DEBUG(dbgs() << "Adjust block:\n"
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<< " - name: " << BB->getName() << "\n"
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<< " - number: " << BB->getNumber() << "\n"
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<< " - function: " << MF.getName() << "\n"
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<< " - blocks: " << MF.getNumBlockIDs() << "\n");
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for(unsigned i = BBNum + 1, e = MF.getNumBlockIDs(); i < e; ++i) {
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// Get the offset and known bits at the end of the layout predecessor.
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// Include the alignment of the current block.
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const Align Align = MF.getBlockNumbered(i)->getAlignment();
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const unsigned Offset = BBInfo[i - 1].postOffset(Align);
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const unsigned KnownBits = BBInfo[i - 1].postKnownBits(Align);
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// This is where block i begins. Stop if the offset is already correct,
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// and we have updated 2 blocks. This is the maximum number of blocks
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// changed before calling this function.
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if (i > BBNum + 2 &&
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BBInfo[i].Offset == Offset &&
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BBInfo[i].KnownBits == KnownBits)
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break;
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BBInfo[i].Offset = Offset;
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BBInfo[i].KnownBits = KnownBits;
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}
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}
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} // end namespace llvm
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