Artem Belevich ed0bd7024b [NVPTX] Added intrinsics for atom.gen.{sys|cta}.* instructions. ... These are only available on sm_60+ GPUs. Differential Revision: https://reviews.llvm.org/D24943 llvm-svn: 282607		2016-09-28 17:25:38 +00:00
..
access-non-generic.ll	[NVPTX] Switch nvptx-use-infer-addrspace to true.	2016-08-19 20:46:45 +00:00
add-128bit.ll
addrspacecast-gvar.ll
addrspacecast.ll	[NVPTX] Switch nvptx-use-infer-addrspace to true.	2016-08-19 20:46:45 +00:00
aggr-param.ll
aggregate-return.ll	[NVPTX] deal with all aggregate return types.	2016-07-20 18:39:52 +00:00
alias.ll	[CUDA] Die gracefully when trying to output an LLVM alias.	2016-01-23 21:12:20 +00:00
annotations.ll
arg-lowering.ll
arithmetic-fp-sm20.ll
arithmetic-int.ll	[NVPTX] expand mul_lohi to mul_lo and mul_hi	2016-01-22 19:47:26 +00:00
atomics-with-scope.ll	[NVPTX] Added intrinsics for atom.gen.{sys|cta}.* instructions.	2016-09-28 17:25:38 +00:00
atomics.ll
bfe.ll
branch-fold.ll
bug17709.ll
bug21465.ll	[NVPTX] Renamed NVPTXLowerKernelArgs -> NVPTXLowerArgs. NFC.	2016-07-20 21:44:07 +00:00
bug22246.ll
bug22322.ll	[NVPTX] Implement llvm.fabs.f32, llvm.max.f32, etc.	2016-09-09 21:07:26 +00:00
bug26185-2.ll	[NVPTX] Fix sign/zero-extending ldg/ldu instruction selection	2016-05-02 18:12:02 +00:00
bug26185.ll	[NVPTX] Handle ldg created from sign-/zero-extended load	2016-04-05 12:38:01 +00:00
bypass-div.ll
call-with-alloca-buffer.ll	Fix NVPTX/call-with-alloca-buffer.ll after r276777.	2016-07-26 18:28:33 +00:00
callchain.ll
calling-conv.ll
combine-min-max.ll
compare-int.ll
constant-vectors.ll
convergent-mir-call.ll	[NVPTX] Use different, convergent MIs for convergent calls.	2016-03-01 19:24:03 +00:00
convert-fp.ll
convert-int-sm20.ll
ctlz.ll
ctpop.ll
cttz.ll
debug-file-loc.ll	[PR27284] Reverse the ownership between DICompileUnit and DISubprogram.	2016-04-15 15:57:41 +00:00
disable-opt.ll	[NVPTX] Disable performance optimizations when OptLevel==None	2016-02-04 04:15:36 +00:00
div-ri.ll
envreg.ll
extloadv.ll
fast-math.ll
fma-assoc.ll
fma-disable.ll
fma.ll
fp16.ll
fp-contract.ll
fp-literals.ll
function-align.ll
generic-to-nvvm-ir.ll	DebugInfo: New metadata representation for global variables.	2016-09-13 01:12:59 +00:00
generic-to-nvvm.ll
global-addrspace.ll
global-ctor-empty.ll	[CUDA] Die if we ask the NVPTX backend to emit a global ctor/dtor.	2016-01-30 01:07:38 +00:00
global-ctor.ll	[CUDA] Die if we ask the NVPTX backend to emit a global ctor/dtor.	2016-01-30 01:07:38 +00:00
global-dtor.ll	[CUDA] Die if we ask the NVPTX backend to emit a global ctor/dtor.	2016-01-30 01:07:38 +00:00
global-ordering.ll
global-visibility.ll	[NVPTX] Do not emit .hidden or .protected directives as they are not allowed by PTX.	2016-01-15 23:57:53 +00:00
globals_init.ll
globals_lowering.ll
gvar-init.ll
half.ll
i1-global.ll
i1-int-to-fp.ll
i1-param.ll
i8-param.ll
imad.ll
implicit-def.ll
inline-asm.ll
intrin-nocapture.ll
intrinsic-old.ll	NVPTX: Remove the legacy ptx intrinsics	2016-07-07 16:40:17 +00:00
intrinsics.ll
isspacep.ll
ld-addrspace.ll
ld-generic.ll
ldg-invariant.ll	[NVPTX] Use ldg for explicitly invariant loads.	2016-09-11 01:39:04 +00:00
ldparam-v4.ll
ldu-i8.ll
ldu-ldg.ll
ldu-reg-plus-offset.ll
lit.local.cfg
load-sext-i1.ll
load-with-non-coherent-cache.ll
LoadStoreVectorizer.ll	[NVPTX] Enable the load-store vectorizer on nvptx.	2016-07-20 22:11:36 +00:00
local-stack-frame.ll
loop-vectorize.ll
lower-aggr-copies.ll
lower-alloca.ll
lower-kernel-ptr-arg.ll	[NVPTX] Improve lowering of byval args of device functions.	2016-07-20 18:39:47 +00:00
machine-sink.ll
MachineSink-call.ll	[NVPTX] Annotate call machine instructions as calls.	2016-02-17 17:46:50 +00:00
MachineSink-convergent.ll	NVPTX: Replace uses of cuda.syncthreads with nvvm.barrier0	2016-07-06 20:02:45 +00:00
managed.ll
math-intrins.ll	[NVPTX] Implement llvm.fabs.f32, llvm.max.f32, etc.	2016-09-09 21:07:26 +00:00
misaligned-vector-ldst.ll
module-inline-asm.ll
mulwide.ll
noduplicate-syncthreads.ll	NVPTX: Replace uses of cuda.syncthreads with nvvm.barrier0	2016-07-06 20:02:45 +00:00
nounroll.ll
nvcl-param-align.ll
nvvm-reflect-module-flag.ll	[NVPTX] Read __CUDA_FTZ from module flags in NVVMReflect.	2016-04-01 01:09:07 +00:00
nvvm-reflect.ll
param-align.ll	[NVPTX] Make sure we adjust alignment at all call sites	2016-07-18 21:58:48 +00:00
pr13291-i1-store.ll
pr16278.ll
pr17529.ll
refl1.ll
reg-copy.ll
reg-types.ll	[NVPTX] Use untyped (.b) integer registers in PTX.	2016-08-12 22:02:19 +00:00
rotate.ll
rsqrt.ll
sched1.ll
sched2.ll
sext-in-reg.ll
sext-params.ll
shfl.ll	[NVPTX] Add intrinsics for shfl instructions.	2016-06-09 20:04:08 +00:00
shift-parts.ll
simple-call.ll
sm-version-20.ll
sm-version-21.ll
sm-version-30.ll
sm-version-32.ll
sm-version-35.ll
sm-version-37.ll
sm-version-50.ll
sm-version-52.ll
sm-version-53.ll
sm-version-60.ll	[NVPTX] Add sm_60, sm_61, sm_62 targets to LLVM.	2016-07-06 21:06:10 +00:00
sm-version-61.ll	[NVPTX] Add sm_60, sm_61, sm_62 targets to LLVM.	2016-07-06 21:06:10 +00:00
sm-version-62.ll	[NVPTX] Add sm_60, sm_61, sm_62 targets to LLVM.	2016-07-06 21:06:10 +00:00
speculative-execution-divergent-target.ll	Move divergent-target test into CodeGen/NVPTX because it requires an NVPTX target.	2016-04-15 01:20:52 +00:00
st-addrspace.ll
st-generic.ll
surf-read-cuda.ll
surf-read.ll
surf-write-cuda.ll
surf-write.ll
symbol-naming.ll	Have a single way for creating unique value names.	2015-11-22 00:16:24 +00:00
TailDuplication-convergent.ll	NVPTX: Replace uses of cuda.syncthreads with nvvm.barrier0	2016-07-06 20:02:45 +00:00
tex-read-cuda.ll
tex-read.ll
texsurf-queries.ll
tuple-literal.ll
vec8.ll
vec-param-load.ll
vector-args.ll
vector-call.ll
vector-compare.ll
vector-global.ll
vector-loads.ll
vector-select.ll
vector-stores.ll
weak-global.ll
weak-linkage.ll
zero-cs.ll	llvm/test/CodeGen/NVPTX/zero-cs.ll: Relax an expression to match in -Asserts.	2016-09-21 04:43:11 +00:00
zeroext-32bit.ll	Only emit extension for zeroext/signext arguments if type is < 32 bits	2016-06-27 20:22:22 +00:00