1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-24 05:23:45 +02:00
llvm-mirror/test/CodeGen/X86/pr28489.ll
Michael Kuperstein e6e21159a7 [X86] Disable FixupSetCC for CodeGenOpt::None
It is an optimization pass, and should not run at -O0. Especially since Fast RA
will not do the required register coalescing anyway, so it's a loss even from
the optimization standpoint.

This also works around (but doesn't quite fix) PR28489.

llvm-svn: 275099
2016-07-11 20:40:44 +00:00

16 lines
393 B
LLVM

; ; RUN: llc < %s -mtriple=i686-pc-linux -O0 | FileCheck %s
declare void @g(i32, i1)
;CHECK-LABEL: f:
;CHECK: cmpxchg8b
;CHECK: sete %cl
;CHECK: movzbl %cl
define void @f(i64* %arg, i64 %arg1) {
entry:
%tmp5 = cmpxchg i64* %arg, i64 %arg1, i64 %arg1 seq_cst seq_cst
%tmp7 = extractvalue { i64, i1 } %tmp5, 1
%tmp9 = zext i1 %tmp7 to i32
call void @g(i32 %tmp9, i1 %tmp7)
ret void
}