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llvm-mirror/test/CodeGen/X86/setcc-narrowing.ll
Michael Kuperstein 3262b6a145 Recommit r274692 - [X86] Transform setcc + movzbl into xorl + setcc
xorl + setcc is generally the preferred sequence due to the partial register
stall setcc + movzbl suffers from. As a bonus, it also encodes one byte smaller.
This fixes PR28146.

The original commit tried inserting an 8bit-subreg into a GR32 (not GR32_ABCD)
which was not appreciated by fast regalloc on 32-bit.

llvm-svn: 274802
2016-07-07 22:50:23 +00:00

19 lines
431 B
LLVM

; RUN: llc < %s -mtriple=i686-apple-darwin | FileCheck %s
; PR17338
@t1.global = internal global i64 -1, align 8
define i32 @t1() nounwind ssp {
entry:
; CHECK-LABEL: t1:
; CHECK: xorl %eax, %eax
; CHECK-NEXT: cmpl $0, _t1.global
; CHECK-NEXT: setne %al
; CHECK-NEXT: ret
%0 = load i64, i64* @t1.global, align 8
%and = and i64 4294967295, %0
%cmp = icmp sgt i64 %and, 0
%conv = zext i1 %cmp to i32
ret i32 %conv
}