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e2f3b489b8
D20859 and D20860 attempted to replace the SSE (V)CVTTPS2DQ and VCVTTPD2DQ truncating conversions with generic IR instead. It turns out that the behaviour of these intrinsics is different enough from generic IR that this will cause problems, INF/NAN/out of range values are guaranteed to result in a 0x80000000 value - which plays havoc with constant folding which converts them to either zero or UNDEF. This is also an issue with the scalar implementations (which were already generic IR and what I was trying to match). This patch changes both scalar and packed versions back to using x86-specific builtins. It also deals with the other scalar conversion cases that are runtime rounding mode dependent and can have similar issues with constant folding. A companion clang patch is at D22105 Differential Revision: https://reviews.llvm.org/D22106 llvm-svn: 275981
35 lines
1.3 KiB
LLVM
35 lines
1.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+sse | FileCheck %s --check-prefix=X64
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; NOTE: This should use IR equivalent to what is generated by clang/test/CodeGen/sse-builtins.c
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define <4 x float> @test_mm_cvtsi64_ss(<4 x float> %a0, i64 %a1) nounwind {
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; X64-LABEL: test_mm_cvtsi64_ss:
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; X64: # BB#0:
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; X64-NEXT: cvtsi2ssq %rdi, %xmm0
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; X64-NEXT: retq
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%res = call <4 x float> @llvm.x86.sse.cvtsi642ss(<4 x float> %a0, i64 %a1)
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ret <4 x float> %res
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}
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declare <4 x float> @llvm.x86.sse.cvtsi642ss(<4 x float>, i64) nounwind readnone
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define i64 @test_mm_cvtss_si64(<4 x float> %a0) nounwind {
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; X64-LABEL: test_mm_cvtss_si64:
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; X64: # BB#0:
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; X64-NEXT: cvtss2si %xmm0, %rax
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; X64-NEXT: retq
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%res = call i64 @llvm.x86.sse.cvtss2si64(<4 x float> %a0)
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ret i64 %res
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}
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declare i64 @llvm.x86.sse.cvtss2si64(<4 x float>) nounwind readnone
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define i64 @test_mm_cvttss_si64(<4 x float> %a0) nounwind {
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; X64-LABEL: test_mm_cvttss_si64:
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; X64: # BB#0:
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; X64-NEXT: cvttss2si %xmm0, %rax
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; X64-NEXT: retq
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%res = call i64 @llvm.x86.sse.cvttss2si64(<4 x float> %a0)
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ret i64 %res
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}
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declare i64 @llvm.x86.sse.cvttss2si64(<4 x float>) nounwind readnone
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