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81066d4513
As discussed in the RFC <http://lists.llvm.org/pipermail/llvm-dev/2018-October/126690.html>, 64-bit RISC-V has i64 as the only legal integer type. This patch introduces patterns to support codegen of the new instructions introduced in RV64I: addiw, addiw, subw, sllw, slliw, srlw, srliw, sraw, sraiw, ld, sd. Custom selection code is needed for srliw as SimplifyDemandedBits will remove lower bits from the mask, meaning the obvious pattern won't work: def : Pat<(sext_inreg (srl (and GPR:$rs1, 0xffffffff), uimm5:$shamt), i32), (SRLIW GPR:$rs1, uimm5:$shamt)>; This is sufficient to compile and execute all of the GCC torture suite for RV64I other than those files using frameaddr or returnaddr intrinsics (LegalizeDAG doesn't know how to promote the operands - a future patch addresses this). When promoting i32 sltu/sltiu operands, it would be more efficient to use sign-extension rather than zero-extension for RV64. A future patch adds a hook to allow this. Differential Revision: https://reviews.llvm.org/D52977 llvm-svn: 347973
309 lines
6.5 KiB
LLVM
309 lines
6.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32I
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV64I
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; These tests are identical to those in alu32.ll but operate on i8. They check
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; that legalisation of these non-native types doesn't introduce unnecessary
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; inefficiencies.
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define i8 @addi(i8 %a) nounwind {
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; RV32I-LABEL: addi:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi a0, a0, 1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: addi:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi a0, a0, 1
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; RV64I-NEXT: ret
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%1 = add i8 %a, 1
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ret i8 %1
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}
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define i8 @slti(i8 %a) nounwind {
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; RV32I-LABEL: slti:
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; RV32I: # %bb.0:
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; RV32I-NEXT: slli a0, a0, 24
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; RV32I-NEXT: srai a0, a0, 24
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; RV32I-NEXT: slti a0, a0, 2
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: slti:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a0, a0, 56
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; RV64I-NEXT: srai a0, a0, 56
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; RV64I-NEXT: slti a0, a0, 2
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; RV64I-NEXT: ret
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%1 = icmp slt i8 %a, 2
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%2 = zext i1 %1 to i8
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ret i8 %2
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}
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define i8 @sltiu(i8 %a) nounwind {
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; RV32I-LABEL: sltiu:
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; RV32I: # %bb.0:
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; RV32I-NEXT: andi a0, a0, 255
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; RV32I-NEXT: sltiu a0, a0, 3
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: sltiu:
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; RV64I: # %bb.0:
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; RV64I-NEXT: andi a0, a0, 255
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; RV64I-NEXT: sltiu a0, a0, 3
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; RV64I-NEXT: ret
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%1 = icmp ult i8 %a, 3
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%2 = zext i1 %1 to i8
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ret i8 %2
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}
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define i8 @xori(i8 %a) nounwind {
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; RV32I-LABEL: xori:
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; RV32I: # %bb.0:
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; RV32I-NEXT: xori a0, a0, 4
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: xori:
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; RV64I: # %bb.0:
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; RV64I-NEXT: xori a0, a0, 4
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; RV64I-NEXT: ret
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%1 = xor i8 %a, 4
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ret i8 %1
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}
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define i8 @ori(i8 %a) nounwind {
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; RV32I-LABEL: ori:
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; RV32I: # %bb.0:
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; RV32I-NEXT: ori a0, a0, 5
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: ori:
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; RV64I: # %bb.0:
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; RV64I-NEXT: ori a0, a0, 5
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; RV64I-NEXT: ret
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%1 = or i8 %a, 5
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ret i8 %1
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}
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define i8 @andi(i8 %a) nounwind {
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; RV32I-LABEL: andi:
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; RV32I: # %bb.0:
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; RV32I-NEXT: andi a0, a0, 6
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: andi:
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; RV64I: # %bb.0:
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; RV64I-NEXT: andi a0, a0, 6
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; RV64I-NEXT: ret
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%1 = and i8 %a, 6
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ret i8 %1
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}
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define i8 @slli(i8 %a) nounwind {
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; RV32I-LABEL: slli:
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; RV32I: # %bb.0:
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; RV32I-NEXT: slli a0, a0, 7
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: slli:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a0, a0, 7
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; RV64I-NEXT: ret
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%1 = shl i8 %a, 7
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ret i8 %1
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}
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define i8 @srli(i8 %a) nounwind {
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; RV32I-LABEL: srli:
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; RV32I: # %bb.0:
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; RV32I-NEXT: andi a0, a0, 192
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; RV32I-NEXT: srli a0, a0, 6
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: srli:
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; RV64I: # %bb.0:
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; RV64I-NEXT: andi a0, a0, 192
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; RV64I-NEXT: srli a0, a0, 6
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; RV64I-NEXT: ret
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%1 = lshr i8 %a, 6
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ret i8 %1
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}
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define i8 @srai(i8 %a) nounwind {
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; RV32I-LABEL: srai:
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; RV32I: # %bb.0:
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; RV32I-NEXT: slli a0, a0, 24
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; RV32I-NEXT: srai a0, a0, 29
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: srai:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a0, a0, 56
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; RV64I-NEXT: srai a0, a0, 61
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; RV64I-NEXT: ret
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%1 = ashr i8 %a, 5
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ret i8 %1
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}
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define i8 @add(i8 %a, i8 %b) nounwind {
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; RV32I-LABEL: add:
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; RV32I: # %bb.0:
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; RV32I-NEXT: add a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: add:
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; RV64I: # %bb.0:
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; RV64I-NEXT: add a0, a0, a1
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; RV64I-NEXT: ret
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%1 = add i8 %a, %b
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ret i8 %1
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}
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define i8 @sub(i8 %a, i8 %b) nounwind {
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; RV32I-LABEL: sub:
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; RV32I: # %bb.0:
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; RV32I-NEXT: sub a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: sub:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sub a0, a0, a1
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; RV64I-NEXT: ret
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%1 = sub i8 %a, %b
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ret i8 %1
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}
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define i8 @sll(i8 %a, i8 %b) nounwind {
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; RV32I-LABEL: sll:
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; RV32I: # %bb.0:
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; RV32I-NEXT: sll a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: sll:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sll a0, a0, a1
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; RV64I-NEXT: ret
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%1 = shl i8 %a, %b
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ret i8 %1
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}
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define i8 @slt(i8 %a, i8 %b) nounwind {
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; RV32I-LABEL: slt:
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; RV32I: # %bb.0:
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; RV32I-NEXT: slli a1, a1, 24
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; RV32I-NEXT: srai a1, a1, 24
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; RV32I-NEXT: slli a0, a0, 24
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; RV32I-NEXT: srai a0, a0, 24
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; RV32I-NEXT: slt a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: slt:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a1, a1, 56
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; RV64I-NEXT: srai a1, a1, 56
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; RV64I-NEXT: slli a0, a0, 56
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; RV64I-NEXT: srai a0, a0, 56
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; RV64I-NEXT: slt a0, a0, a1
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; RV64I-NEXT: ret
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%1 = icmp slt i8 %a, %b
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%2 = zext i1 %1 to i8
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ret i8 %2
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}
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define i8 @sltu(i8 %a, i8 %b) nounwind {
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; RV32I-LABEL: sltu:
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; RV32I: # %bb.0:
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; RV32I-NEXT: andi a1, a1, 255
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; RV32I-NEXT: andi a0, a0, 255
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; RV32I-NEXT: sltu a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: sltu:
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; RV64I: # %bb.0:
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; RV64I-NEXT: andi a1, a1, 255
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; RV64I-NEXT: andi a0, a0, 255
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; RV64I-NEXT: sltu a0, a0, a1
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; RV64I-NEXT: ret
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%1 = icmp ult i8 %a, %b
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%2 = zext i1 %1 to i8
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ret i8 %2
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}
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define i8 @xor(i8 %a, i8 %b) nounwind {
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; RV32I-LABEL: xor:
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; RV32I: # %bb.0:
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; RV32I-NEXT: xor a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: xor:
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; RV64I: # %bb.0:
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; RV64I-NEXT: xor a0, a0, a1
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; RV64I-NEXT: ret
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%1 = xor i8 %a, %b
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ret i8 %1
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}
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define i8 @srl(i8 %a, i8 %b) nounwind {
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; RV32I-LABEL: srl:
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; RV32I: # %bb.0:
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; RV32I-NEXT: andi a0, a0, 255
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; RV32I-NEXT: srl a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: srl:
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; RV64I: # %bb.0:
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; RV64I-NEXT: andi a0, a0, 255
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; RV64I-NEXT: srl a0, a0, a1
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; RV64I-NEXT: ret
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%1 = lshr i8 %a, %b
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ret i8 %1
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}
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define i8 @sra(i8 %a, i8 %b) nounwind {
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; RV32I-LABEL: sra:
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; RV32I: # %bb.0:
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; RV32I-NEXT: slli a0, a0, 24
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; RV32I-NEXT: srai a0, a0, 24
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; RV32I-NEXT: sra a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: sra:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a0, a0, 56
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; RV64I-NEXT: srai a0, a0, 56
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; RV64I-NEXT: sra a0, a0, a1
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; RV64I-NEXT: ret
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%1 = ashr i8 %a, %b
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ret i8 %1
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}
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define i8 @or(i8 %a, i8 %b) nounwind {
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; RV32I-LABEL: or:
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; RV32I: # %bb.0:
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; RV32I-NEXT: or a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: or:
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; RV64I: # %bb.0:
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; RV64I-NEXT: or a0, a0, a1
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; RV64I-NEXT: ret
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%1 = or i8 %a, %b
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ret i8 %1
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}
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define i8 @and(i8 %a, i8 %b) nounwind {
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; RV32I-LABEL: and:
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; RV32I: # %bb.0:
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; RV32I-NEXT: and a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: and:
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; RV64I: # %bb.0:
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; RV64I-NEXT: and a0, a0, a1
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; RV64I-NEXT: ret
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%1 = and i8 %a, %b
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ret i8 %1
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}
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