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103277308c
Summary:
When lowering global address, lower the base as a TargetGlobal first then
create an SDNode for the offset separately and chain it to the address calculation
This optimization will create a DAG where the base address of a global access will
be reused between different access. The offset can later be folded into the immediate
part of the memory access instruction.
With this optimization we generate:
lui a0, %hi(s)
addi a0, a0, %lo(s) ; shared base address.
addi a1, zero, 20 ; 2 instructions per access.
sw a1, 44(a0)
addi a1, zero, 10
sw a1, 8(a0)
addi a1, zero, 30
sw a1, 80(a0)
Instead of:
lui a0, %hi(s+44) ; 3 instructions per access.
addi a1, zero, 20
sw a1, %lo(s+44)(a0)
lui a0, %hi(s+8)
addi a1, zero, 10
sw a1, %lo(s+8)(a0)
lui a0, %hi(s+80)
addi a1, zero, 30
sw a1, %lo(s+80)(a0)
Which will save one instruction per access.
Reviewers: asb, apazos
Reviewed By: asb
Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang, apazos, asb, llvm-commits
Differential Revision: https://reviews.llvm.org/D46989
llvm-svn: 332641
198 lines
5.0 KiB
LLVM
198 lines
5.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32I
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; Check indexed and unindexed, sext, zext and anyext loads
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define i32 @lb(i8 *%a) nounwind {
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; RV32I-LABEL: lb:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lb a1, 0(a0)
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; RV32I-NEXT: lb a0, 1(a0)
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; RV32I-NEXT: ret
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%1 = getelementptr i8, i8* %a, i32 1
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%2 = load i8, i8* %1
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%3 = sext i8 %2 to i32
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; the unused load will produce an anyext for selection
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%4 = load volatile i8, i8* %a
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ret i32 %3
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}
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define i32 @lh(i16 *%a) nounwind {
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; RV32I-LABEL: lh:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lh a1, 0(a0)
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; RV32I-NEXT: lh a0, 4(a0)
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; RV32I-NEXT: ret
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%1 = getelementptr i16, i16* %a, i32 2
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%2 = load i16, i16* %1
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%3 = sext i16 %2 to i32
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; the unused load will produce an anyext for selection
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%4 = load volatile i16, i16* %a
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ret i32 %3
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}
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define i32 @lw(i32 *%a) nounwind {
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; RV32I-LABEL: lw:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lw a1, 0(a0)
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; RV32I-NEXT: lw a0, 12(a0)
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; RV32I-NEXT: ret
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%1 = getelementptr i32, i32* %a, i32 3
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%2 = load i32, i32* %1
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%3 = load volatile i32, i32* %a
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ret i32 %2
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}
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define i32 @lbu(i8 *%a) nounwind {
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; RV32I-LABEL: lbu:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lbu a1, 0(a0)
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; RV32I-NEXT: lbu a0, 4(a0)
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; RV32I-NEXT: add a0, a0, a1
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; RV32I-NEXT: ret
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%1 = getelementptr i8, i8* %a, i32 4
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%2 = load i8, i8* %1
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%3 = zext i8 %2 to i32
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%4 = load volatile i8, i8* %a
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%5 = zext i8 %4 to i32
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%6 = add i32 %3, %5
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ret i32 %6
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}
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define i32 @lhu(i16 *%a) nounwind {
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; RV32I-LABEL: lhu:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lhu a1, 0(a0)
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; RV32I-NEXT: lhu a0, 10(a0)
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; RV32I-NEXT: add a0, a0, a1
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; RV32I-NEXT: ret
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%1 = getelementptr i16, i16* %a, i32 5
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%2 = load i16, i16* %1
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%3 = zext i16 %2 to i32
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%4 = load volatile i16, i16* %a
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%5 = zext i16 %4 to i32
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%6 = add i32 %3, %5
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ret i32 %6
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}
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; Check indexed and unindexed stores
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define void @sb(i8 *%a, i8 %b) nounwind {
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; RV32I-LABEL: sb:
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; RV32I: # %bb.0:
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; RV32I-NEXT: sb a1, 6(a0)
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; RV32I-NEXT: sb a1, 0(a0)
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; RV32I-NEXT: ret
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store i8 %b, i8* %a
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%1 = getelementptr i8, i8* %a, i32 6
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store i8 %b, i8* %1
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ret void
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}
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define void @sh(i16 *%a, i16 %b) nounwind {
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; RV32I-LABEL: sh:
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; RV32I: # %bb.0:
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; RV32I-NEXT: sh a1, 14(a0)
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; RV32I-NEXT: sh a1, 0(a0)
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; RV32I-NEXT: ret
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store i16 %b, i16* %a
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%1 = getelementptr i16, i16* %a, i32 7
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store i16 %b, i16* %1
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ret void
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}
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define void @sw(i32 *%a, i32 %b) nounwind {
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; RV32I-LABEL: sw:
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; RV32I: # %bb.0:
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; RV32I-NEXT: sw a1, 32(a0)
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; RV32I-NEXT: sw a1, 0(a0)
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; RV32I-NEXT: ret
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store i32 %b, i32* %a
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%1 = getelementptr i32, i32* %a, i32 8
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store i32 %b, i32* %1
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ret void
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}
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; Check load and store to an i1 location
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define i32 @load_sext_zext_anyext_i1(i1 *%a) nounwind {
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; RV32I-LABEL: load_sext_zext_anyext_i1:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lb a1, 0(a0)
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; RV32I-NEXT: lbu a1, 1(a0)
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; RV32I-NEXT: lbu a0, 2(a0)
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; RV32I-NEXT: sub a0, a0, a1
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; RV32I-NEXT: ret
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; sextload i1
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%1 = getelementptr i1, i1* %a, i32 1
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%2 = load i1, i1* %1
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%3 = sext i1 %2 to i32
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; zextload i1
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%4 = getelementptr i1, i1* %a, i32 2
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%5 = load i1, i1* %4
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%6 = zext i1 %5 to i32
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%7 = add i32 %3, %6
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; extload i1 (anyext). Produced as the load is unused.
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%8 = load volatile i1, i1* %a
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ret i32 %7
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}
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define i16 @load_sext_zext_anyext_i1_i16(i1 *%a) nounwind {
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; RV32I-LABEL: load_sext_zext_anyext_i1_i16:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lb a1, 0(a0)
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; RV32I-NEXT: lbu a1, 1(a0)
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; RV32I-NEXT: lbu a0, 2(a0)
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; RV32I-NEXT: sub a0, a0, a1
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; RV32I-NEXT: ret
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; sextload i1
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%1 = getelementptr i1, i1* %a, i32 1
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%2 = load i1, i1* %1
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%3 = sext i1 %2 to i16
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; zextload i1
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%4 = getelementptr i1, i1* %a, i32 2
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%5 = load i1, i1* %4
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%6 = zext i1 %5 to i16
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%7 = add i16 %3, %6
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; extload i1 (anyext). Produced as the load is unused.
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%8 = load volatile i1, i1* %a
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ret i16 %7
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}
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; Check load and store to a global
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@G = global i32 0
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define i32 @lw_sw_global(i32 %a) nounwind {
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; RV32I-LABEL: lw_sw_global:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a2, %hi(G)
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; RV32I-NEXT: lw a1, %lo(G)(a2)
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; RV32I-NEXT: sw a0, %lo(G)(a2)
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; RV32I-NEXT: addi a2, a2, %lo(G)
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; RV32I-NEXT: lw a3, 36(a2)
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; RV32I-NEXT: sw a0, 36(a2)
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; RV32I-NEXT: mv a0, a1
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; RV32I-NEXT: ret
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%1 = load volatile i32, i32* @G
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store i32 %a, i32* @G
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%2 = getelementptr i32, i32* @G, i32 9
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%3 = load volatile i32, i32* %2
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store i32 %a, i32* %2
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ret i32 %1
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}
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; Ensure that 1 is added to the high 20 bits if bit 11 of the low part is 1
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define i32 @lw_sw_constant(i32 %a) nounwind {
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; RV32I-LABEL: lw_sw_constant:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a2, 912092
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; RV32I-NEXT: lw a1, -273(a2)
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; RV32I-NEXT: sw a0, -273(a2)
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; RV32I-NEXT: mv a0, a1
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; RV32I-NEXT: ret
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%1 = inttoptr i32 3735928559 to i32*
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%2 = load volatile i32, i32* %1
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store i32 %a, i32* %1
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ret i32 %2
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}
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