Sander de Smalen b22701bd85 [AArch64][SVE] Asm: Support for contiguous LD1 (scalar+scalar) load instructions. ... This is patch [4/4] in a series to add assembler/disassembler support for SVE's contiguous LD1 (scalar+scalar) instructions: - Patch [1/4]: https://reviews.llvm.org/D45687 - Patch [2/4]: https://reviews.llvm.org/D45688 - Patch [3/4]: https://reviews.llvm.org/D45689 - Patch [4/4]: https://reviews.llvm.org/D45690 Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D45690 llvm-svn: 330423		2018-04-20 12:52:01 +00:00
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AArch64Disassembler.cpp	[AArch64][SVE] Asm: Support for contiguous LD1 (scalar+scalar) load instructions.	2018-04-20 12:52:01 +00:00
AArch64Disassembler.h
AArch64ExternalSymbolizer.cpp
AArch64ExternalSymbolizer.h
CMakeLists.txt
LLVMBuild.txt